# US 12,761,687 B2 · Optimal timer array

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- Number: US 12,761,687 B2
- Document ID: US12761687B2
- Status: Granted
- Kind: B2
- Application number: 18/904,770
- Filed: 2024-10-02
- Published: 2025-01-23
- Granted: 2026-10-13
- Earliest claimed: 2021-02-22
- Assignees: pSemi Corporation
- Applicants: pSemi Corporation
- Inventors: Gerald Alcorn
- Web page: https://patentgrep.com/patent/US12761687B2

## CPC

- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G05B 19/045: using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
- H03K 19/17716: {with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register (H03K19/17712 takes precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

## Claims

### Claim 1

A digital circuit, comprising:
a timer array configured to generate a plurality of timed triggers, the timer array comprising:
a reference counter operating from a reference clock;
a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a respective target offset value of the reference counter; and
a target translation logic block that is configured to translate, for each timed trigger of the plurality of timed triggers, a current value of the reference counter to an offset value based on a number of reference clock counts to the respective target offset value of the reference counter.

### Claim 2 (depends on 1)

The digital circuit of claim 1, wherein the respective target offset value of the reference counter is at an offset equal to the number of reference clock counts from a value of the reference counter at the time of request of the each timed trigger.

### Claim 3 (depends on 1)

The digital circuit of claim 1, wherein:
the reference counter is free running, and
the time of request of a first timed trigger of the plurality of timed triggers is different from the time of request of a second timed trigger of the plurality of timed triggers.

### Claim 4 (depends on 1)

The digital circuit of claim 1, wherein the timer array further comprises:
an array of a plurality of target registers configured to store the respective target offset value corresponding to the each timed trigger of the plurality of timed triggers.

### Claim 5 (depends on 1)

The digital circuit of claim 1, wherein the timer array further comprises:
a set valid flag logic block that is configured to:
set a respective valid flag at a time of request of the each timed trigger, and reset the respective valid flag at a time of completion of the each timed trigger.

### Claim 6 (depends on 5)

The digital circuit of claim 5, wherein the timer array further comprises:
an array of a plurality of valid flag registers configured to store a value of the respective valid flag of the each timed trigger of the plurality of timed triggers.

### Claim 7 (depends on 1)

The digital circuit of claim 1, wherein the timer array further comprises:
an array of a plurality of comparators configured to compare a current value of the reference counter to the respective target offset value corresponding to the each timed trigger of the plurality of timed triggers.

### Claim 8 (depends on 1)

The digital circuit of claim 1, wherein the reference counter comprises:
a) a binary counter; b) a gray code counter; c) a ring counter; d) a ripple counter; or e) a cyclic code counter.

### Claim 9 (depends on 1)

The digital circuit of claim 1, further comprising:
a slave interface circuit configured to communicate with a master device over an interface bus.

### Claim 10 (depends on 9)

The digital circuit of claim 9, wherein:
the interface bus is according to the MIPI RFFE interface.

### Claim 11 (depends on 9)

A radio frequency (RF) device, comprising:
an RF circuit configured to process an RF signal; and
a digital circuit configured to communicate with a master device separate from the RF device, the digital circuit being a digital circuit according to claim 9.

### Claim 12 (depends on 11)

The RF device of claim 11, wherein the RF circuit comprises one or more of: a) a power amplifier; b) a low-noise amplifier; c) a filter; d) a matching circuit; e) an RF switch; or f) an antenna tuner circuit.

### Claim 13 (depends on 11)

A radio frequency (RF) module, comprising an RF device according to claim 11.

### Claim 14 (depends on 11)

A radio frequency (RF) multi-die module, comprising:
a plurality of dies, wherein each die of the plurality of dies comprises an RF device according to claim 11.

### Claim 15 (depends on 11)

A radio frequency (RF) frontend system, comprising one or more RF devices according to claim 11.

### Claim 16

A radio frequency (RF) device, comprising:
an RF circuit configured to process an RF signal; and
a digital circuit configured to communicate with a master device separate from the RF device, the digital circuit comprising:
a timer array configured to generate a plurality of timed triggers for synchronization of events between the master device and the RF circuit, the timer array comprising:
a reference counter operating from a reference clock;
a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a target offset value of the reference counter; and
a target translation logic block that is configured to translate, for each time trigger of the plurality of timed triggers, a current value of the reference counter to an offset value based on a number of reference clock counts to the target offset value of the reference counter.

### Claim 17

A method for generating a plurality of timed trigger events, the method comprising:
providing a reference counter operating from a reference clock;
translating a requested timed trigger event of the plurality of timed trigger events into a target offset value of the reference counter;
translating a current value of the reference counter to an offset value based on a number of reference clock counts to the target offset value of the reference counter; and
generating the requested timed trigger event when the offset value is equal to the target offset value.

### Claim 18 (depends on 17)

The method according to claim 17, further comprising:
establishing a plurality of timers by assigning to each timer a target offset register; and
storing the target offset value of the requested timed trigger event to the target offset register of a respective timer of the plurality timers.

### Claim 19 (depends on 17)

The method according to claim 17, further comprising:
establishing a plurality of timers by assigning to each timer a set valid flag register; and
setting a valid flag indicative of the requested timed trigger event and storing a value of the valid flag to the set valid flag register of the respective timer of the plurality of timers.

### Claim 20 (depends on 18)

The method according to claim 18, further comprising:
resetting the valid flag at a time of completion of the requested timed trigger event.