Outlier integrated circuit detection method and outlier integrated circuit detection system by using machine learning frameworks

An outlier integrated circuit (IC) detection system for use in a post silicon test flow, comprising:

• a training stage unit configured to receive first measured data of a first IC set;
• an inference stage unit configured to receive second measured data of a second IC set, wherein the second measured data comprises wafer sort (WS) process measured data and/or final test (FT) process measured data;
• an extreme gradient boosting (XGBoost) unit;
• a memory;
• a Mahalanobis distance unit;
• and
• an outlier IC identification unit;
• wherein the first measured data is trained by using the training stage unit, the trained first measured data is used for generating a training model by the XGBoost unit, the training model is saved in the memory, the second measured data received by the inference stage unit is inputted to the memory, predicted data of the second IC set is generated by using the training model according to the second measured data, a bivariate dataset distribution of the second IC set is generated according to the predicted data and the second measured data, a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set is generated by the Mahalanobis distance unit according to yield loss configurations of the second IC set for identifying at least one outlier IC, and at least one outlier IC is identified from the second IC set by the outlier IC identification unit when at least one position of at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance, the first IC set and the second IC set are different, and the at least one outlier IC is withdrawn from the second IC set.