Copper rings for BGA count reduction in small form factor packages
AssigneeIntel Corporation
InventorsKavitha Nagarajan, Min Suet Lim, Eng Huat Goh, Telesphor Kamgaing, Chee Kheong Yoon, Jooi Wah Wong, Chu Aun Lim
Life of this patent
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Abstract
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die. In an embodiment, a package substrate is coupled to the die. In an embodiment, a ring is provided under the package substrate. In an embodiment, the ring comprises a conductive material. In an embodiment, the electronic package further comprises balls outside of the ring.
Claims19
An electronic package, comprising:
- a die;
- a package substrate coupled to the die;
- a ring under the package substrate, wherein the ring comprises a conductive material, and wherein the die is entirely within an outermost perimeter of the ring from a plan view perspective;
- balls outside of the ring;
- and
- a capacitor within the ring, wherein a standoff height of the capacitor is less than a standoff height of the ring.
A package substrate, comprising:
- a substrate with a first surface and a second surface opposite from the first surface;
- a die coupled to the first surface of the package substrate;
- an array of balls on the second surface of the substrate, wherein the array of balls includes a cavity;
- a first ring inside the cavity, wherein the die is entirely within an outermost perimeter of the first ring from a plan view perspective;
- a second ring inside the cavity and around the first ring, wherein the second ring includes a plurality of segments, wherein each segment is electrically isolated from each other, and wherein the plurality of segments are configured to be held at different voltages during operation of the package substrate;
- and
- capacitors in the cavity.
An electronic system, comprising:
- a board;
- a package substrate coupled to the board, wherein the package substrate comprises:
- a first ring between the package substrate and the board;
- a second ring between the package substrate and the board, wherein the second ring is around the first ring, wherein the first ring is configured to be grounded, and wherein the second ring comprises a plurality of segments that are configured to be held at different voltages;
- and
- balls between the package substrate and the board, wherein the balls are outside of the second ring;
- and
- a die coupled to the package substrate, wherein the die is entirely within an outermost perimeter of the first ring from a plan view perspective.
An electronic package, comprising:
- a die;
- a package substrate coupled to the die;
- a ring under the package substrate, wherein the ring comprises a conductive material, and wherein the die is entirely within an outermost perimeter of the ring from a plan view perspective;
- balls outside of the ring;
- and
- a capacitor within the ring, wherein a standoff height of the capacitor is greater than a standoff height of the ring.
A package substrate, comprising:
- a substrate with a first surface and a second surface opposite from the first surface;
- a die coupled to the first surface of the package substrate;
- an array of balls on the second surface of the substrate, wherein the array of balls includes a cavity;
- a first ring inside the cavity, wherein the die is entirely within an outermost perimeter of the first ring from a plan view perspective, and wherein the first ring is configured to be held at a ground voltage during operation of the package substrate;
- a second ring inside the cavity and around the first ring;
- and
- capacitors in the cavity.
Dependencies are inferred from the claim text.