US 12,757,795 B2 · Semiconductor package and method for manufacturing a semiconductor package

Abstract

The present application discloses a semiconductor package and a method for manufacturing the semiconductor package. The semiconductor package includes a first dielectric layer, a first redistribution layer (RDL) disposed on a first surface of the first dielectric layer, a first bonding layer disposed on the first RDL, a plurality of bottom dies attached to the first bonding layer, a second dielectric layer filling gaps between the bottom dies, a plurality of conductive pillars disposed in the second dielectric layer without contacting the bottom dies, a second RDL disposed on the second dielectric layer and the bottom dies, a second bonding layer disposed on the second RDL, a plurality of top dies attached to the second bonding layer, a third dielectric layer filling gaps between the top dies, and a plurality of solder bumps disposed on a second surface of the first dielectric layer.

Claims20

Dependent claims

A semiconductor package comprising:

a first dielectric layer;
a first redistribution layer (RDL) disposed on a first surface of the first dielectric layer;
a first bonding layer disposed on the first RDL;
a plurality of bottom dies having bonding layers attached to the first bonding layer;
a second dielectric layer filling gaps between the bottom dies;
a plurality of conductive pillars disposed in the second dielectric layer without contacting the bottom dies;
a second RDL disposed on the second dielectric layer and coupled the conductive pillars and a plurality of through silicon vias (TSVs) formed in backsides of the bottom dies;
a second bonding layer disposed on the second RDL;
a plurality of top dies having bonding layers attached to the second bonding layer;
a third dielectric layer filling gaps between the top dies;
and
a plurality of solder bumps disposed on a second surface of the first dielectric layer and coupled to the first RDL through openings of the first dielectric layer.

9 more elements

A semiconductor package comprising:

a first dielectric layer;
a first redistribution layer (RDL) disposed on a first surface of the first dielectric layer, wherein the first RDL comprises:
a first reticle region;
and
a second reticle region adjacent to the first reticle region,
wherein the first reticle region has a first interconnect layout pattern different from a second interconnect layout pattern of the second reticle region;
a first bonding layer disposed on the first RDL;
a plurality of bottom dies having bonding layers attached to the first bonding layer;
a second dielectric layer filling gaps between the bottom dies;
a plurality of conductive pillars disposed in the second dielectric layer without contacting the bottom dies;
a second RDL disposed on the second dielectric layer and coupled the conductive pillars and a plurality of through silicon vias (TSVs) formed in backsides of the bottom dies;
a second bonding layer disposed on the second RDL;
a plurality of top dies having bonding layers attached to the second bonding layer;
and
a third dielectric layer filling gaps between the top dies.

12 more elements

Dependencies are inferred from the claim text.

Semiconductor package and method for manufacturing a semiconductor package

Life of this patent

Semiconductor package and method for manufacturing a semiconductor package

Life of this patent

Abstract

Claims20