Semiconductor module arrangement

A power semiconductor module arrangement, comprising:

• a substrate comprising a dielectric insulation layer and a first metallization layer arranged on a first side of the dielectric insulation layer, wherein the first metallization layer comprises a plurality of different sections that are separate and distinct from each other;
• and
• a plurality of semiconductor bodies arranged on the first metallization layer, and comprising a first sub-group of semiconductor bodies and a second sub-group of semiconductor bodies, wherein semiconductor bodies of the first sub-group of semiconductor bodies differ from semiconductor bodies of the second sub-group of semiconductor bodies,
• wherein each of the plurality of semiconductor bodies comprises a control electrode and a controllable load path between a first load electrode and a second load electrode,
• wherein the first load electrode of each of the plurality of semiconductor bodies is electrically coupled to a first section of the first metallization layer,
• wherein the second load electrode of each of the semiconductor bodies of the first sub-group of semiconductor bodies are electrically coupled to a second section of the first metallization layer, and the second load electrode of each of the semiconductor bodies of the second sub-group of semiconductor bodies are electrically coupled to a third section of the first metallization layer,
• wherein the control electrode of each of the semiconductor bodies of the first sub-group of semiconductor bodies are electrically coupled to a fourth section of the first metallization layer, and the control electrode of each of the semiconductor bodies of the second sub-group of semiconductor bodies are electrically coupled to a fifth section of the first metallization layer,
• wherein the first sub-group of semiconductor bodies is symmetrical to the second sub-group of semiconductor bodies, and
• wherein the power semiconductor module arrangement further comprises:
• a housing, wherein the substrate is arranged inside or forms a bottom of the housing;
• and
• a plurality of terminal elements, each comprising a first end and a second end,
• wherein the first end of each of a first sub-group of terminal elements is electrically and mechanically coupled to the first section of the first metallization layer,
• wherein the first end of each of a second sub-group of terminal elements is electrically and mechanically coupled to the second section of the first metallization layer,
• wherein the first end of each of a third sub-group of terminal elements is electrically and mechanically coupled to the third section of the first metallization layer,
• wherein the first end of each of a fourth sub-group of terminal elements is electrically and mechanically coupled to the fourth section of the first metallization layer,
• wherein the first end of each of a fifth sub-group of terminal elements is electrically and mechanically coupled to the fifth section of the first metallization layer, and
• wherein the second end of each of the plurality of terminal elements extends to an outside of the housing.

A power semiconductor module arrangement, comprising:

• a substrate comprising a dielectric insulation layer and a first metallization layer arranged on a first side of the dielectric insulation layer, wherein the first metallization layer comprises a plurality of different sections that are separate and distinct from each other;
• and
• a plurality of semiconductor bodies arranged on the first metallization layer, and comprising a first sub-group of semiconductor bodies and a second sub-group of semiconductor bodies, wherein semiconductor bodies of the first sub-group of semiconductor bodies differ from semiconductor bodies of the second sub-group of semiconductor bodies,
• wherein each of the plurality of semiconductor bodies comprises a control electrode and a controllable load path between a first load electrode and a second load electrode,
• wherein the first load electrode of each of the plurality of semiconductor bodies is electrically coupled to a first section of the first metallization layer,
• wherein the second load electrode of each of the semiconductor bodies of the first sub-group of semiconductor bodies are electrically coupled to a second section of the first metallization layer, and the second load electrode of each of the semiconductor bodies of the second sub-group of semiconductor bodies are electrically coupled to a third section of the first metallization layer,
• wherein the control electrode of each of the semiconductor bodies of the first sub-group of semiconductor bodies are electrically coupled to a fourth section of the first metallization layer, and the control electrode of each of the semiconductor bodies of the second sub-group of semiconductor bodies are electrically coupled to a fifth section of the first metallization layer,
• wherein the first sub-group of semiconductor bodies is symmetrical to the second sub-group of semiconductor bodies, and
• wherein the power semiconductor module arrangement further comprises a plurality of freewheeling elements arranged on the first metallization layer, and comprising a first sub-group of freewheeling elements and a second sub-group of freewheeling elements, wherein freewheeling elements of the first sub-group of freewheeling elements differ from freewheeling elements of the second sub-group of freewheeling elements, wherein:
• the first sub-group of freewheeling elements is electrically coupled to the first sub-group of semiconductor bodies, and
• the second sub-group of freewheeling elements is electrically coupled to the second sub-group of semiconductor bodies.