Silicon nitride layer under a copper pad
AssigneeIntel Corporation
InventorsBrandon C. Marin, Suddhasattwa Nad, Srinivas V. Pietambaram, Gang Duan, Jeremy D. Ecton, Kristof Darmawikarta, Sameer Paital
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AssigneeIntel Corporation
InventorsBrandon C. Marin, Suddhasattwa Nad, Srinivas V. Pietambaram, Gang Duan, Jeremy D. Ecton, Kristof Darmawikarta, Sameer Paital
Estimating the term…
Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.
A substrate comprising:
A package comprising:
A method comprising:
Dependencies are inferred from the claim text.