Package structure including a package substrate and methods of forming the same

A method of forming a package substrate, the method comprising:

• forming a plurality of bonding pads on a carrier substrate;
• forming a dielectric layer structure on the plurality of bonding pads, wherein the dielectric layer structure includes a first dielectric layer and a second dielectric layer;
• forming a metal interconnect structure including a plurality of first metal vias in the first dielectric layer and a plurality of second metal vias in the second dielectric layer, wherein the plurality of first metal vias and the plurality of second metal vias have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer;
• and
• forming a plurality of metal pillars on an upper surface of the second dielectric layer, wherein the metal interconnect structure extends from the plurality of bonding pads to the plurality of metal pillars, wherein the forming of the plurality of metal pillars comprises:
• forming a plurality of C4 metal bumps on the upper surface of the second dielectric layer;
• forming a metal dam adjacent the plurality of C4 metal bumps on the upper surface of the second dielectric layer;
• and
• forming a chip-scale package (CSP) pad adjacent the metal dam on the upper surface of the second dielectric layer, wherein a diameter of the CSP pad is greater than a diameter of the plurality of C4 metal bumps.

A package structure comprising:

• a package substrate, comprising:
• a dielectric layer structure including a first dielectric layer and a second dielectric layer;
• a plurality of ball grid array (BGA) bonding pads located at a lower surface of the first dielectric layer;
• a plurality of metal pillars located on an upper surface of the second dielectric layer, wherein the plurality of metal pillars comprise:
• a plurality of C4 metal bumps;
• a metal dam adjacent the plurality of C4 metal bumps on the upper surface of the second dielectric layer;
• and
• a plurality of chip-scale package pads adjacent the metal dam on the upper surface of the second dielectric layer, wherein a diameter of the plurality of chip-scale package pads is greater than a diameter of the plurality of C4 metal bumps;
• and
• a metal interconnect structure extending from the BGA bonding pads to the plurality of metal pillars and including a plurality of first metal vias in the first dielectric layer and a plurality of second metal vias in the second dielectric layer, wherein the plurality of first metal vias and the plurality of second metal vias have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer;
• an interposer module on the plurality of C4 metal bumps, wherein the interposer module includes an interposer and a plurality of semiconductor devices on the interposer, and wherein the plurality of semiconductor devices are electrically coupled to the BGA bonding pads through the metal interconnect structure;
• a chip-scale package on the plurality of chip-scale package pads and electrically coupled to the BGA bonding pads through the metal interconnect structure;
• and
• a package lid located over the interposer module and the chip-scale package and including a package lid foot portion attached to the package substrate.