Semiconductor packages, semiconductor device and method for manufacturing a semiconductor package

A method for manufacturing a semiconductor package comprising:

• receiving a silicon interposer;
• forming a plurality of through silicon vias (TSVs) within the silicon interposer;
• forming a redistribution layer (RDL) on a first surface of the silicon interposer;
• receiving a plurality of computation nodes wherein each of the computation nodes comprises a computation die, and each of computation dies of the computation nodes comprises a plurality of micro bumps;
• disposing the computation nodes on the RDL, comprising bonding the computation dies of the computation nodes to the RDL through the micro bumps, wherein the RDL is between the computation nodes and the silicon interposer;
• grinding a backside of the silicon interposer to expose the plurality of TSVs;
• and
• forming a plurality of bumps on a second surface of the silicon interposer and coupled to the plurality of TSVs, wherein the bumps are coupled to the RDL through the TSVs;
• wherein:
• each two adjacent computation nodes of the computation nodes are coupled to each other through the RDL;
• and
• from a top view, the RDL comprises interconnect structures distributed in portions that overlap the computation nodes and portions free from overlapping the computation nodes;
• wherein the step of forming the RDL comprises:
• forming a plurality of first rectangular regions of the RDL by utilizing a first series of masks;
• and
• forming a plurality of second rectangular regions of the RDL by utilizing a second series of masks;
• wherein the first rectangular regions have same sizes and same patterns of interconnect structures, the second rectangular regions have same sizes and same patterns of interconnect structures, and each of the first rectangular regions is adjacent to at least one of the second rectangular regions.

A semiconductor package comprising:

• a silicon interposer;
• a redistribution layer (RDL) disposed on a first surface of the silicon interposer;
• a plurality of computation nodes disposed on the RDL, each of the computation nodes comprising a computation die, wherein the RDL is between the computation nodes and the silicon interposer, and each of computation dies of the computation nodes comprises a plurality of micro bumps, and the computation dies are bonded to the RDL through the micro bumps;
• a plurality of through silicon vias (TSVs) passing through the silicon interposer;
• and
• a plurality of bumps disposed on a second surface of the silicon interposer and coupled to the RDL through the TSVs;
• wherein:
• each two adjacent computation nodes of the computation nodes are coupled to each other through the RDL;
• from the top view, the RDL comprises interconnect structures distributed in portions that overlap the computation nodes and portions free from overlapping the computation nodes;
• from the top view, the RDL comprises a plurality of first rectangular regions formed with a first series of masks and a plurality of second rectangular regions formed with a second series of masks, and each of the computation nodes overlaps at least one of the first rectangular regions and at least one of the second rectangular regions;
• and
• the first rectangular regions have same sizes and same patterns of interconnect structures, the second rectangular regions have same sizes and same patterns of interconnect structures, patterns of the first rectangular regions are different from patterns of the second rectangular regions, and each of the first rectangular regions is adjacent to at least one of the second rectangular regions.