US 12,757,748 B2Granted

Aligned via and trace formation using multi-tone phoitomasks and multi-layer photosensitive stacks

AssigneeIntel Corporation

InventorsChanghua Liu, Leonel R. Arana, Jeremy D. Ecton, Suddhasattwa Nad, Brandon Christian Marin

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Abstract

Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity layer, a medium-photosensitivity layer, and a low-photosensitivity layer are applied to a substrate and exposed at the same time with use of a multi-tone mask. After being developed, one layer forms a mold for a first via, one layer forms a mold for a conductive trace and a second via, and one layer forms an overhang over the position for the second via. The molds formed by the photosensitive layers are filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the region under the overhang forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.

Claims20

Dependent claims

A method comprising:

applying a first layer to a substrate, wherein the first layer comprises a photoimageable dielectric (PID) material;
applying a second layer to the first layer, wherein the second layer comprises a PID material or a photoresist material;
applying a third layer to the second layer, wherein the third layer comprises a photoresist material;
exposing the first layer, the second layer, and the third layer with electromagnetic radiation with use of a multi-tone photomask, wherein the electromagnetic radiation through one or more light gray regions of the multi-tone photomask exposes two but not three of the first layer, second layer, and third layer, and wherein the electromagnetic radiation through one or more dark gray regions of the multi-tone photomask exposes only one of the first layer, second layer, and third layer;
developing the first layer, the second layer, and the third layer,
wherein the developed first layer defines a first mold with a first via region,
wherein the developed second layer defines a second mold with a conductive trace region and a second via region,
wherein the developed third layer comprises an overhang region that extends over the second via region;
filling the mold defined by the first layer and the mold defined by the second layer with a conductive infill;
and
applying an etchant to the conductive infill, wherein the etchant etches the conductive infill from a top surface of the conductive infill to create a conductive trace in the conductive trace region, wherein the etchant laterally etches the conductive infill under the overhang region to create a via in the second via region, wherein the etched conductive infill comprises a first via in the first via region, a conductive trace in the conductive trace region, and a second via in the second via region.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/351,537Filed 18 Jun 2021
Published: US 2022/0406618 A122 Dec 2022
Granted: 6 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 70/095
Of insulating or insulated package substrates, or of interposers, or of redistribution layers: of vias therein
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 20/081
Of dielectric parts thereof: by forming openings in the dielectric parts
H10W 70/611
Insulating or insulated package substrates; Interposers; Redistribution layers: for connecting multiple chips together