Inverted memory stack

A memory stack, comprising:

• a plurality of memory layers stacked one on top of another;
• a cooling solution located at one end of the memory stack of the plurality of memory layers;
• a first digital device layer located between a first two of the plurality of memory layers;
• and
• a second digital device layer located between a second two of the plurality of memory layers.

A memory stack, comprising:

• a plurality of memory layers stacked one on top of another;
• at least two digital device layers separately interleaved with and electrically interconnected to the plurality of memory layers;
• and
• a cooling solution located at one end of the memory stack of the plurality of memory layers and the at least two digital device layers.

An electronic system, comprising:

• at least one memory stack, each comprising
• a first digital device layer,
• a cooling solution on a first side of the first digital device layer,
• a second digital device layer, and
• a plurality of memory layers having at least a first memory layer and a second memory layer, the first memory layer disposed between the first digital layer and the cooling solution, the second memory layer disposed between the first and second digital layers;
• and
• a system on a chip (SoC) electrically coupled to the at least one memory stack.