Semiconductor device and methods of formation

A method of forming a semiconductor device, comprising:

• forming a first dielectric layer;
• forming an etch stop layer over the first dielectric layer;
• forming a second dielectric layer over the etch stop layer,
• wherein the first dielectric layer, the etch stop layer, and the second dielectric layer are included in a back end of line (BEOL) region of the semiconductor device;
• forming a BEOL resistor structure, included in the first dielectric layer, comprising:
• a resistive layer;
• a contact structure on the resistive layer;
• a capping layer on the contact structure,
• a sealing layer on a sidewall of the contact structure,
• wherein the sealing layer is between the resistive layer and an overhang portion of the capping layer, and
• wherein the sealing layer is included on four sides of the contact structure;
• an interconnect via structure in the first dielectric layer and extending into a portion of the contact structure,
• wherein a height of a top surface of the sealing layer in the semiconductor device is greater relative to a height of a bottom surface of the interconnect via in the semiconductor device;
• and
• a metallization layer connected with the interconnect via structure,
• wherein the metallization layer extends through the etch stop layer and the second dielectric layer.

A method of forming a semiconductor device, comprising:

• forming a first dielectric layer;
• forming an etch stop layer over the first dielectric layer;
• forming a second dielectric layer over the etch stop layer,
• wherein the first dielectric layer, the etch stop layer, and the second dielectric layer are included in a back end of line (BEOL) region of the semiconductor device;
• forming a BEOL resistor structure, included in the first dielectric layer, comprising:
• a resistive layer,
• a contact structure on the resistive layer,
• a capping layer on the contact structure,
• a sealing layer on a sidewall of the contact structure,
• wherein the sealing layer is between the resistive layer and an overhang portion of the capping layer, and
• wherein the sealing layer comprises at least one of:
• tungsten (W), or
• molybdenum (Mo;
• an interconnect via structure in the first dielectric layer and extending into a portion of the contact structure,
• wherein a height of a top surface of the sealing layer in the semiconductor device is greater relative to a height of a bottom surface of the interconnect via in the semiconductor device;
• and
• a metallization layer connected with the interconnect via structure,
• wherein the metallization layer extends through the etch stop layer and the second dielectric layer.