Power gating transistor for BSPDN

A microelectronic architecture comprising:

• a logic device;
• a header gate transistor located adjacent to a first side of the logic device, wherein the header gate transistor has a parallel orientation to the logic device, wherein the header gate transistor is connected to a VSS source or a VDD source, wherein the VSS source or the VDD source is connected to the frontside of the header gate transistor;
• and
• a footer gate transistor located adjacent to a second side of the logic device, wherein the footer gate transistor has parallel orientation to the logic device, wherein the first side and the second side are opposite sides of the logic device, wherein the footer gate transistor is connected to a VSS source or a VDD source, wherein the footer gate transistor is connected to a different source than the header gate transistor, wherein the logic device is connected to the VSS source and the VDD source through either footer gate transistor and the header gate transistor, wherein the VSS source or the VDD source is connected to the frontside of the footer gate transistor, wherein the header gate transistor, the footer gate transistor, and the logic device are located on the same level on top of a backside interlayer dielectric layer.