Method and structure for forming landing for backside power distribution network

A semiconductor comprising:

• a sacrificial layer located directly between a first substrate layer and a second substrate layer, wherein the sacrificial layer has a first thickness, wherein the second substrate layer has a second thickness, wherein the second thickness is larger than the first thickness;
• a source/drain located on top of the second substrate layer;
• a dielectric landing pad located within the sacrificial layer, wherein the dielectric landing pad extends horizontally within a void of the sacrificial layer, wherein the dielectric landing pad fills the entire void within the sacrificial layer;
• a vertical dielectric liner that extends off the dielectric landing pad, wherein the dielectric landing pad is integrally formed with the vertical dielectric liner;
• a frontside contact comprised of a first section and a second section, wherein the first section of the frontside contact is located on top of the source/drain, wherein the second section of the frontside contact is a via that extends downwards past and through the dielectric landing pad, wherein the vertical dielectric liner extends along a vertical sidewall of the second section of the frontside contact.