US 12,757,710 B2Granted

Semiconductor device structure including forksheet transistors and methods of forming the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsHong-Chih Chen, Chun-Sheng Liang, Yu-San Chien, Wei-Chih Kao

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Abstract

A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall. The structure also includes a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type. The structure further includes a gate bridge contact disposed on the first dielectric wall, and a gate via contact disposed on the gate bridge contact.

Claims20

Dependent claims

A method for forming a semiconductor device structure, comprising:

forming first, second, third, and fourth fin structures from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers, the second fin structure includes a second plurality of semiconductor layers, the third fin structure includes a third plurality of semiconductor layers, and the fourth fin structure includes a fourth plurality of semiconductor layers, and wherein each of the first, second, third, and fourth plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers;
forming a first dielectric wall between the first fin structure and the second fin structure;
forming a second dielectric wall between the third fin structure and the fourth fin structure;
forming a sacrificial gate stack over a portion of the first, second, third, and fourth fin structures, and over a portion of the first and second dielectric walls;
removing a portion of the first, second, third, and fourth fin structures not covered by the sacrificial gate stack;
removing the sacrificial gate stack to expose portions of the first, second, third, and fourth fin structures;
selectively removing the second semiconductor layers of the first, second, third, and fourth plurality of semiconductor layers;
surrounding a first gate electrode layer over at least three surfaces of each of the first semiconductor layers of the third plurality of semiconductor layers, wherein the first gate electrode layer has a first conductivity type;
surrounding a second gate electrode layer over at least three surfaces of each of the first semiconductor layers of the fourth plurality of semiconductor layers, wherein the second gate electrode layer has a second conductivity type opposite the first conductivity type;
performing a planarization operation after formation of the first and second gate electrode layers such that top surfaces of the first and second dielectric walls and top surfaces of the first and second gate electrode layers are substantially co-planar;
forming a cut metal gate (CMG) structure extending through an entire thickness of at least one of the first and second gate electrode layers to electrically isolate adjacent gate regions on opposite sides of the respective first and second dielectric wall;
forming a gate bridge contact on the second dielectric wall after formation of the CMG structure, the gate bridge contact electrically coupling gate electrode layers having a same conductivity type;
and
forming a gate via contact on the gate bridge contact.

11 more elements

A method for forming a semiconductor device structure, comprising:

forming a first dielectric wall that laterally separates n-type and p-type forksheet transistor regions;
forming a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall;
forming a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall;
forming a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, and the first gate electrode layer having a first conductivity type;
forming a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, and the second gate electrode layer having a second conductivity type opposite the first conductivity type;
forming a cut metal gate (CMG) structure extending through an entire thickness of the second gate electrode layer, the CMG structure separating the second gate electrode layer into electrically isolated gate regions such that the first gate electrode layer and the second gate electrode layer are electrically isolated across the first dielectric wall;
forming a gate bridge contact on the first dielectric wall after formation of the CMG structure, wherein the gate bridge contact electrically couples gate electrode layers having the same conductivity type;
and
forming a gate via contact on the gate bridge contact.

6 more elements

A method for forming a semiconductor device structure, comprising:

forming a first dielectric wall;
forming a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall;
forming a second dielectric wall in parallel with the first dielectric wall;
forming a plurality of second semiconductor layers vertically stacked and extending outwardly from both sides of the second dielectric wall;
forming a third dielectric wall in parallel with the first dielectric wall;
forming a plurality of third semiconductor layers vertically stacked and extending outwardly from a first side of the third dielectric wall;
forming a gate structure over a portion of the first, second, and third dielectric walls, the gate structure comprising oppositely doped gate electrode regions separated by at least one cut metal gate (CMG) structure extending through an entire thickness of a gate electrode layer;
forming a source/drain contact over a portion of the first dielectric wall and in contact with an epitaxial source/drain feature;
forming a metal on gate bridge contact over the gate structure and in contact with a portion of the gate structure and the source/drain contact;
and
forming a gate bridge contact over a portion of the gate structure and in contact with the second dielectric wall, wherein the gate bridge contact is formed after formation of the CMG structure and electrically couples with gate electrode regions having a same conductivity type.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/099,952Filed 22 Jan 2023 · us provisional application
Priority: 29 Nov 2022
Published: US 2024/0178128 A130 May 2024
Granted: 6 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10D 30/6729
Thin-film transistors [TFT]: characterised by the electrodes
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
H10D 62/121
Nanowire, nanosheet or nanotube semiconductor bodies: oriented parallel to substrates