Semiconductor packages with wettable flanks and related methods
AssigneeSemiconductor Components Industries, LLC
InventorsNam Khong Then, Hui Min Ler, Phillip Celaya, Chee Hiong Chew
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Abstract
Implementations of a leadframe for a semiconductor package may include a half-etched gate lead directly coupled to a gate tie bar; a half-etched source lead directly coupled to a source tie bar; and a die flag directly coupled to at least two die flag tie bars. The gate tie bar and the source tie bar may be configured to enable electroplating of a flank of the half-etched gate lead and the half-etched source lead.
Claims20
A leadframe for a semiconductor package comprising:
- a half-etched gate lead directly coupled to a gate tie bar;
- a half-etched source lead directly coupled to a source tie bar;
- and
- a die flag directly coupled to at least two die flag tie bars;
- wherein, the gate tie bar and the source tie bar are configured to enable electroplating of a flank of the half-etched gate lead and the half-etched source lead.
A method of forming a semiconductor package comprising:
- half etching a gate lead directly coupled to a gate tie bar;
- half etching at least one source lead directly coupled to a source tie bar;
- and
- half etching a portion of a die flag directly coupled to at least two die flag tie bars;
- cutting the gate lead and the at least one source lead;
- electroplating a flank of the gate lead using only the gate tie bar;
- and
- electroplating a flank of the at least one source lead using only the source tie bar.
A method of forming a semiconductor package comprising:
- providing a gate lead directly coupled to a gate tie bar;
- providing a source lead directly coupled to a source tie bar;
- maximizing a size of a die flag by half-etching the gate lead, half-etching the source lead, and half-etching the die flag, the die flag being directly coupled to at least two die flag tie bars;
- and
- cutting the gate lead and the source lead.
Dependencies are inferred from the claim text.