Method for fabricating semiconductor device with protection liner for bit line

A method for fabricating a semiconductor device, comprising:

• forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate;
• forming a gate dielectric layer lining the trench;
• forming a barrier layer over the gate dielectric layer;
• forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, wherein forming the gate electrode layer comprises:
• depositing a first gate electrode material over the gate dielectric layer and the top surface of the semiconductor substrate, wherein a first gap is surrounded by the first gate electrode material;
• etching the first gate electrode material to widen the first gap such that a first opening is surrounded by a remaining portion of the first gate electrode material, wherein a top width of the first opening is greater than a top width of the first gap;
• depositing a second gate electrode material over the remaining portion of the first gate electrode material;
• and
• forming a bit line structure over a S/D region of the semiconductor substrate, wherein the bit line structure includes a protection liner having a U-shaped profile and in direct contact with an upper portion of the gate dielectric layer.

A method for fabricating a semiconductor device, comprising:

• forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate;
• forming a gate dielectric layer lining the trench;
• and
• forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, wherein forming the gate electrode layer comprises:
• depositing a first gate electrode material over the gate dielectric layer and the top surface of the semiconductor substrate, wherein a first gap is surrounded by the first gate electrode material;
• etching the first gate electrode material to reduce a thickness of the first gate electrode material over the top surface of the semiconductor substrate;
• depositing a second gate electrode material over a remaining portion of the first gate electrode material after the first gate electrode material is etched;
• and
• etching the second gate electrode material to reduce a thickness of the second gate electrode material over the top surface of the semiconductor substrate;
• and
• forming a bit line structure over a S/D region of the semiconductor substrate, wherein the bit line structure includes a protection liner having a U-shaped profile and in direct contact with an upper portion of the gate dielectric layer;
• wherein the first gap is enlarged during the etching of the first gate electrode material such that a first opening is surrounded by the remaining portion of the first gate electrode material before the second gate electrode material is deposited, and a top width of the first opening is greater than a top width of the first gap.