Display substrate and display device

A display substrate, comprising:

• a base substrate;
• and
• a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer which are disposed on the base substrate in sequence,
• wherein the first insulating layer comprises a first conductive structure;
• the second conductive layer comprises a second conductive structure;
• the first conductive structure comprises a bottom surface close to the base substrate, a top surface away from the base substrate, and a first side surface located between the bottom surface and the top surface;
• the second insulating layer comprises a first via hole, and the second conductive layer is in contact with the first conductive structure through the first via hole;
• the second conductive structure comprises a first protrusion;
• the first via hole exposes at least a portion of the first side surface of the first conductive structure, and the first protrusion is in contact with the at least portion of the first side surface of the first conductive structure;
• the first insulating layer comprises a first depression structure and a second depression structure spaced apart from each other;
• the first conductive structure further comprises a second side surface located between the bottom surface and the top surface, and the first side surface is opposite to the second side surface;
• and at least a portion of the first conductive structure is respectively located in the first depression structure and the second depression structure.

A display substrate, comprising:

• a base substrate;
• and
• a first metal layer, a second metal layer, a first conductive layer, and a second conductive layer which are disposed on the base substrate in sequence,
• wherein the display substrate further comprises a first sub-pixel and a second sub-pixel which are on the base substrate and adjacent in a first direction;
• the first sub-pixel comprises a first pixel circuit, and the second sub-pixel comprises a second pixel circuit;
• the first pixel circuit and the second pixel circuit each comprise a capacitor which comprises a first capacitor electrode in the second metal layer and a second capacitor electrode in the first metal layer;
• the first capacitor electrode of the first pixel circuit and the first capacitor electrode of the second pixel circuit are connected to each other into an integrated capacitor electrode block;
• the capacitor electrode block has a first opening and a second opening;
• an orthographic projection of the first opening on the base substrate is overlapped with an orthographic projection of the second capacitor electrode of the first pixel circuit on the base substrate, and an orthographic projection of the second opening on the base substrate is overlapped with an orthographic projection of the second capacitor electrode of the second pixel circuit on the base substrate;
• and an area of the orthographic projection of the first opening on the base substrate is different from an area of the orthographic projection of the second opening on the base substrate;
• wherein the second conductive layer comprises a reset voltage line, a first data line, a second data line, a first power line, and a second power line which are extended along a second direction, and the first direction is different from the second direction;
• each of the first pixel circuit and the second pixel circuit comprises a driving transistor and a data writing transistor;
• the reset voltage line is configured to provide a reset voltage for pixel electrodes or gate electrodes of the driving transistors of the first pixel circuit and the second pixel circuit;
• the first data line and the second data line are configured to provide data voltages for the data writing transistors of the first pixel circuit and the second pixel circuit, respectively;
• the first power line is configured to provide a power voltage for the driving transistor of the first pixel circuit, and the second power line is configured to provide a power voltage for the driving transistor of the second pixel circuit;
• the reset voltage line is between the first data line and the second data line;
• the first data line and the second data line are both between the first power line and the second power line;
• and
• the first power line and the second power line each have a closed hollowed-out region.