Three-layered stacked image sensor and method of manufacturing the same

A three-layered stacked image sensor comprising:

• a first chip at a top position and comprising a photodiode, a transfer gate, a floating diffusion region, and a first wiring layer;
• a second chip at an intermediate position and comprising a source follower gate, a select gate, a reset gate, and a second wiring layer;
• and
• a third chip at a bottom position and comprising an image sensor processor and a third wiring layer,
• the second chip comprising a silicon layer on the second wiring layer, an upper pad on the silicon layer, and a through electrode extending from the second wiring layer through the silicon layer and connected to the upper pad,
• a first pad of the first wiring layer and the upper pad bonded to each other,
• a second pad of the second wiring layer and a third pad of the third wiring layer bonded to each other, and
• a cross-section of an upper portion of the through electrode bonded to the upper pad having an inverted trapezoidal structure.

A three-layered stacked image sensor comprising:

• an upper chip comprising a plurality of pixels arranged in a two-dimensional array structure, a first wiring layer beneath the plurality of pixels, and a color filter and a microlens stacked on each of the plurality of pixels, each of the plurality of pixels comprising a photodiode, a transfer gate, and a floating diffusion region;
• an intermediate chip comprising a source follower gate, a select gate, and a reset gate corresponding to each of the plurality of pixels, a first silicon layer and an upper insulating layer at an upper portion of the intermediate chip, and a second wiring layer at a lower portion of the intermediate chip, the intermediate chip comprising a through electrode extending from the second wiring layer through the first silicon layer and the upper insulating layer, and an upper pad on the through electrode;
• and
• a lower chip comprising an image sensor processor, a third wiring layer at an upper portion of the lower chip, and a second silicon layer at a lower portion of the lower chip,
• the upper chip, the intermediate chip, and the lower chip being sequentially stacked from a top,
• a first pad of the first wiring layer and the upper pad bonded to each other,
• a second pad of the second wiring layer and a third pad of the third wiring layer bonded to each other, and
• a cross-section of a portion of the through electrode corresponding to the upper insulating layer having an inverted trapezoidal structure.