US 12,757,497 B2Granted

Electrostatic discharge (ESD) protection device with a targeted sub-fin etch depth

AssigneeIntel Corporation

InventorsNicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Mauro J. Kobrinsky

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Abstract

An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.

Claims20

Dependent claims

An integrated circuit structure comprising:

a first device comprising (i) a first diffusion region, (ii) a first body comprising semiconductor material extending laterally from the first diffusion region, (iii) a first gate structure on the first body, and (iv) a first sub-fin having a bottom surface directly on a dielectric material, wherein the first diffusion region has a lower section that extends within the first sub-fin below a lower surface of the first gate structure, the lower section of the first diffusion region having a first vertical height;
and
a second device laterally adjacent to the first device, the second device comprising (i) a second diffusion region, (ii) a second body comprising semiconductor material extending laterally from the second diffusion region, (iii) a second gate structure on the second body, and (iv) a second sub-fin having a bottom surface directly on the dielectric material, wherein the second diffusion region has a lower section that extends within the second sub-fin below a lower surface of the second gate structure, the lower section of the second diffusion region having a second vertical height;
wherein the first vertical height is at least 2 nanometers (nm) greater than the second vertical height, and wherein a vertical height of the first sub-fin is greater than a vertical height of the second sub-fin by at least 2 nm.

1 more element

An integrated circuit structure comprising:

a first device comprising (i) a first sub-fin, (ii) a first diffusion region in contact with and extending in part within the first sub-fin, (iii) a second diffusion region, and (iv) a trench comprising dielectric material and laterally between the first and second diffusion regions, wherein a portion of the first diffusion region extending within the first sub-fin has a first height, and wherein a lower section of each of the second diffusion region and the trench, which extends within the first sub-fin, has a height that is within 1 nm of the first height;
and
a second device laterally adjacent to the first device, the second device comprising (i) a second sub-fin, and (ii) a third diffusion region in contact with and extending in part within the second sub-fin, wherein a portion of the third diffusion region extending within the second sub-fin has a second height;
wherein the first height is at least 2 nanometers (nm) greater than the second height.

1 more element

An integrated circuit structure comprising:

a first device comprising (i) a sub-fin, (ii) first one or more diffusion regions in contact with the sub-fin, and (iii) a trench laterally adjacent to the first one or more diffusion regions, the trench comprising dielectric material and having (a) an upper section extending upward from the sub-fin, and (b) a lower section extending within the sub-fin, wherein the lower section of the trench has a first vertical height;
and
a second device laterally adjacent to the first device, the second device comprising (i) a second diffusion region, (ii) a body comprising semiconductor material extending laterally from the second diffusion region, and (iii) a gate structure on the body, wherein the second diffusion region has a lower section that extends below a lower surface of the second gate structure, the lower section of the second diffusion region having a second vertical height;
wherein the first vertical height is at least 2 nanometers (nm) greater than the second vertical height.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/943,815Filed 13 Sep 2022
Published: US 2024/0088134 A114 Mar 2024
Granted: 6 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 89/811
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using FETs as protective elements
H10D 84/013
The components including insulated gates, e.g. IGFETs: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0151
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe