US 12,757,493 B2Granted

Array substrate, manufacturing method thereof, and display panel

AssigneeShenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

InventorChuanbao Luo

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Abstract

An array substrate, its manufacturing method, and a display panel are provided. The array substrate includes a substrate, a first active layer, a source-drain layer, a first gate, a second active layer, and a second gate. The first active layer includes a first channel portion corresponding to the first gate. The second active layer includes a second channel portion corresponding to the second gate. The first active layer and the second active layer are connected in parallel. The source-drain layer and the first channel portion are arranged on the surface of a same layer, so an insulating layer between the source-drain layer and the first active layer is omitted. Additionally, the first active layer directly contacts a source contact portion and a drain contact portion of the source-drain layer, so contact holes between the first active layer and the source-drain layer are omitted, simplifying fabrication of the array substrate.

Claims20

Dependent claims

An array substrate, comprising:

a substrate;
a first active layer disposed on the substrate and comprising a first channel portion, wherein the first active layer comprises two first doped portions disposed on two sides of the first channel portion;
a source-drain layer disposed on the substrate, wherein the source-drain layer and the first channel portion are disposed on a surface of a same layer, and the source-drain layer comprises a source contact portion and a drain contact portion separated from each other, wherein the first channel portion is disposed between the source contact portion and the drain contact portion, and the two first doped portions make electrical contact with the source contact portion and the drain contact portion, respectively;
a first gate disposed on one side of the first active layer away from the substrate, wherein the first gate is disposed corresponding to the first channel portion;
a second active layer disposed on one side of the first gate away from the substrate, wherein the second active layer comprises a second channel portion, and the first channel portion and the second channel portion are separated from each other, wherein the second active layer comprises two second doped portions disposed on two sides of the second channel portion, and the second doped portions are electrically connected to the respectively corresponding first doped portions through first via holes, wherein an ion concentration of the first doped portion is greater than an ion concentration of the second doped portion;
and
a second gate disposed on one side of the second active layer away from the substrate, wherein the second gate is disposed corresponding to the second channel portion;
wherein the first active layer and the second active layer are connected in parallel, and the first active layer directly contacts the source contact portion and the drain contact portion.

5 more elements

An array substrate, comprising:

a substrate;
a first active layer disposed on the substrate and comprising a first channel portion, wherein the first active layer comprises two first doped portions disposed on two sides of the first channel portion;
a source-drain layer disposed on the substrate, wherein the source-drain layer and the first channel portion are disposed on a surface of a same layer, and the source-drain layer comprises a source contact portion and a drain contact portion separated from each other, wherein the first channel portion is disposed between the source contact portion and the drain contact portion, and the two first doped portions make electrical contact with the source contact portion and the drain contact portion, respectively;
a first gate disposed on one side of the first active layer away from the substrate, wherein the first gate is disposed corresponding to the first channel portion;
a second active layer disposed on one side of the first gate away from the substrate, wherein the second active layer comprises a second channel portion, and the first channel portion and the second channel portion are separated from each other, wherein the second active layer comprises two second doped portions disposed on two sides of the second channel portion, the second doped portions are electrically connected to the respectively corresponding first doped portions through first via holes, wherein an ion concentration of the first doped portion is greater than an ion concentration of the second doped portion and a length of the first channel portion is greater than a length of the second channel portion;
and
a second gate disposed on one side of the second active layer away from the substrate, wherein the second gate is disposed corresponding to the second channel portion;
wherein the first active layer and the second active layer are connected in parallel, and the first active layer directly contacts the source contact portion and the drain contact portion.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/496,899Filed 29 Oct 2023
Priority: CN 202311197648.815 Sep 2023
Published: US 2025/0098303 A120 Mar 2025
Granted: 6 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
H10D 86/021
Manufacture or treatment: of multiple TFTs
H10D 86/441
Characterised by multiple TFTs: interconnections, e.g. scanning lines
H10D 86/421
Characterised by multiple TFTs: having a particular composition, shape or crystalline structure of the active layer