US 12,757,490 B2Granted

Display device, semiconductor device, and driving method thereof

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsAtsushi Umezaki, Hajime Kimura

Life of this patent

Estimating the term…

Abstract

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

Claims3

Dependent claims

A semiconductor device comprising:

a pixel area comprising a first pixel, a second pixel, and a third pixel;
and
a driver circuit comprising a first circuit, a second circuit, and a third circuit,
wherein the first circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same conductivity type,
wherein one of a source and a drain of the first transistor is electrically connected to a first line and the other of the source and the drain of the first transistor is electrically connected to a second line,
wherein one of a source and a drain of the second transistor is electrically connected to the second line and the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, the other of the source and the drain of the third transistor is electrically connected to a third line, and a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fourth transistor is electrically connected to a fourth line, and a gate of the fourth transistor is electrically connected to a fifth line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fifth transistor is electrically connected to the third line, and a gate of the fifth transistor is electrically connected to a sixth line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor, the other of the source and the drain of the sixth transistor is electrically connected to the third line, and a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the first line, the other of the source and the drain of the seventh transistor is electrically connected to a seventh line, and a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the second line and a gate of the eighth transistor is electrically connected to the sixth line,
wherein a ratio of the channel width to the channel length of the fifth transistor is smaller than a ratio of the channel width to the channel length of the fourth transistor,
wherein the first circuit is configured to output a signal to the first pixel through the second line,
wherein the second circuit is configured to output a signal to the second pixel through the fourth line, and
wherein the third circuit is configured to output a signal to the third pixel through the sixth line.

14 more elements

A semiconductor device comprising:

a pixel area comprising a first pixel, a second pixel, and a third pixel;
and
a driver circuit comprising a first circuit, a second circuit, and a third circuit,
wherein the first circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same conductivity type,
wherein one of a source and a drain of the first transistor is electrically connected to a first line and the other of the source and the drain of the first transistor is electrically connected to a second line,
wherein one of a source and a drain of the second transistor is electrically connected to the second line and the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, the other of the source and the drain of the third transistor is electrically connected to a third line, and a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fourth transistor is electrically connected to a fourth line, and a gate of the fourth transistor is electrically connected to a fifth line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fifth transistor is electrically connected to the third line, and a gate of the fifth transistor is electrically connected to a sixth line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor, the other of the source and the drain of the sixth transistor is electrically connected to the third line, and a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the first line, the other of the source and the drain of the seventh transistor is electrically connected to a seventh line, and a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the second line and a gate of the eighth transistor is electrically connected to the sixth line,
wherein a ratio of the channel width to the channel length of the fifth transistor is smaller than a ratio of the channel width to the channel length of the fourth transistor,
wherein the other of the source and the drain of the second transistor and the one of the source and the drain of the eighth transistor are configured to be supplied with power supply voltage,
wherein the first circuit is configured to output a signal to the first pixel through the second line,
wherein the second circuit is configured to output a signal to the second pixel through the fourth line, and
wherein the third circuit is configured to output a signal to the third pixel through the sixth line.

15 more elements

A semiconductor device comprising:

a pixel area comprising a first pixel, a second pixel, and a third pixel;
and
a driver circuit comprising a first circuit, a second circuit, and a third circuit,
wherein the first circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same conductivity type,
wherein one of a source and a drain of the first transistor is electrically connected to a first line and the other of the source and the drain of the first transistor is electrically connected to a second line,
wherein one of a source and a drain of the second transistor is electrically connected to the second line and the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, the other of the source and the drain of the third transistor is electrically connected to a third line, and a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fourth transistor is electrically connected to a fourth line, and a gate of the fourth transistor is electrically connected to a fifth line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fifth transistor is electrically connected to the third line, and a gate of the fifth transistor is electrically connected to a sixth line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor, the other of the source and the drain of the sixth transistor is electrically connected to the third line, and a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the first line, the other of the source and the drain of the seventh transistor is electrically connected to a seventh line, and a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the second line and a gate of the eighth transistor is electrically connected to the sixth line,
wherein a ratio of the channel width to the channel length of the fifth transistor is smaller than a ratio of the channel width to the channel length of the fourth transistor,
wherein the first line serves as a clock signal line,
wherein the other of the source and the drain of the second transistor and the one of the source and the drain of the eighth transistor are configured to be supplied with power supply voltage,
wherein the first circuit is configured to output a signal to the first pixel through the second line,
wherein the second circuit is configured to output a signal to the second pixel through the fourth line, and
wherein the third circuit is configured to output a signal to the third pixel through the sixth line.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/219,831Filed 10 Jul 2023 · continuation
Priority: JP 2010-03690223 Feb 2010
Published: US 2023/0352491 A12 Nov 2023
Granted: 6 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G09G 3/20
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes: for presentation of an…
G09G 3/3674
Control of matrices with row and column drivers: details of drivers for scan electrodes
G09G 3/3677
Details of drivers for scan electrodes: suitable for active matrices only

Family

Application13/025,479Parent of this continuation · filed 11 Feb 2011
Application14/085,864Parent of this division · filed 21 Nov 2013
US 8,599,998 B2Parent of this continuation · filed 3 Dec 2013
Application14/885,353Parent of this continuation · filed 16 Oct 2015
Application15/680,348Parent of this continuation · filed 18 Aug 2017
Application16/809,663Parent of this continuation · filed 5 Mar 2020
Application17/087,801Parent of this continuation · filed 3 Nov 2020
US 11,222,906 B2Parent of this continuation · filed 11 Jan 2022
US 2023/0352491 A1Pre-grant publication · published 2 Nov 2023
US 11,749,685 B2Parent of this continuation
Application14/885,353Parent of this division
Application14/085,864Parent of this continuation
US 2011/0204928 A1Published application
US 2014/0077215 A1Published application
US 2016/0043111 A1Published application
US 2017/0365625 A1Published application
US 2020/0203387 A1Published application
US 2021/0074737 A1Published application
US 12,757,490 B2This patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

A semiconductor device comprising:

a pixel area comprising a first pixel, a second pixel, and a third pixel;
and
a driver circuit comprising a first circuit, a second circuit, and a third circuit,
wherein the first circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same conductivity type,
wherein one of a source and a drain of the first transistor is electrically connected to a first line and the other of the source and the drain of the first transistor is electrically connected to a second line,
wherein one of a source and a drain of the second transistor is electrically connected to the second line and the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, the other of the source and the drain of the third transistor is electrically connected to a third line, and a gate of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fourth transistor is electrically connected to a fourth line, and a gate of the fourth transistor is electrically connected to a fifth line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fifth transistor is electrically connected to the third line, and a gate of the fifth transistor is electrically connected to a sixth line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor, the other of the source and the drain of the sixth transistor is electrically connected to the third line, and a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the first line, the other of the source and the drain of the seventh transistor is electrically connected to a seventh line, and a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the second line and a gate of the eighth transistor is electrically connected to the sixth line,
wherein a ratio of the channel width to the channel length of the fifth transistor is smaller than a ratio of the channel width to the channel length of the fourth transistor,
wherein the first circuit is configured to output a signal to the first pixel through the second line,
wherein the second circuit is configured to output a signal to the second pixel through the fourth line, and
wherein the third circuit is configured to output a signal to the third pixel through the sixth line.

14 more elements

Facts

Application

18/219,831Filed 10 Jul 2023 · continuation

Priority

JP 2010-03690223 Feb 2010

Published

US 2023/0352491 A12 Nov 2023

Granted

6 Oct 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G09G 3/20
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes: for presentation of an…
G09G 3/3674
Control of matrices with row and column drivers: details of drivers for scan electrodes
G09G 3/3677
Details of drivers for scan electrodes: suitable for active matrices only

Family

Application13/025,479Parent of this continuation · filed 11 Feb 2011

Application14/085,864Parent of this division · filed 21 Nov 2013

US 8,599,998 B2Parent of this continuation · filed 3 Dec 2013

Application14/885,353Parent of this continuation · filed 16 Oct 2015

Application15/680,348Parent of this continuation · filed 18 Aug 2017

Application16/809,663Parent of this continuation · filed 5 Mar 2020

Application17/087,801Parent of this continuation · filed 3 Nov 2020

US 11,222,906 B2Parent of this continuation · filed 11 Jan 2022

US 2023/0352491 A1Pre-grant publication · published 2 Nov 2023

US 11,749,685 B2Parent of this continuation

Application14/885,353Parent of this division

Application14/085,864Parent of this continuation

US 2011/0204928 A1Published application

US 2014/0077215 A1Published application

US 2016/0043111 A1Published application

US 2017/0365625 A1Published application

US 2020/0203387 A1Published application

US 2021/0074737 A1Published application

US 12,757,490 B2This patent

From the US filing history. Foreign family members aren’t listed.