Enlarged overlap between backside power rail and backside contact

A semiconductor device comprising:

• a first backside power rail below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region;
• a first backside contact connecting the first backside power rail to the first source-drain epitaxy region of the positive field effect transistor (p-FET) region, wherein the first backside contact is vertically aligned with the first source-drain epitaxy region;
• the first backside power rail directly contacts an upper horizontal surface of the first backside contact, a vertical side surface of the first backside contact, and an upper horizontal surface of a gate cut dielectric;
• a second backside power rail directly below and connected to a second source-drain epitaxy region of a negative field effect transistor (n-FET) region;
• a second backside contact connecting the second backside power rail to the second source-drain epitaxy region of the negative field effect transistor (n-FET) region, wherein the second backside contact is vertically aligned with the second source-drain epitaxy region;
• the second backside power rail directly contacts an upper horizontal surface of the second backside contact and the second backside power rail directly contacts a vertical side surface of the second backside contact;
• and
• a high-k dielectric spacer between the first backside power rail and the second backside power rail, wherein the high-k dielectric spacer comprises a k value of greater than 5, and wherein the high-k dielectric spacer is between the n-FET region and the p-FET region.