Cross field effect transistor library cell architecture design
AssigneeAdvanced Micro Devices, Inc.
InventorRichard T. Schultz
Life of this patent
Estimating the term…
Abstract
A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.
Claims20
A method comprising:
- forming, in a first cell of an integrated circuit, a first pair of transistors with channels of different doping polarities configured to receive a first input signal by each transistor of the first pair of transistors;
- forming, in the first cell, a second pair of transistors with channels of different doping polarities configured to receive two different input signals, wherein a transistor of a first doping polarity of the second pair of transistors has a greater length of a gate region than a transistor of the second doping polarity of the first pair of transistors;
- and
- responsive to a potential being applied to an input node of the integrated circuit, conveying a current from the input node to an output node of the integrated circuit through the first cell.
An integrated circuit comprising:
- a first cell comprising:
- a first pair of transistors with channels of different doping polarities configured to receive a first input signal by each transistor of the first pair of transistors;
- a second pair of transistors with channels of different doping polarities configured to receive two different input signals, wherein a transistor of a first doping polarity of the second pair of transistors has a greater length of a gate region than a transistor of the second doping polarity of the first pair of transistors;
- and
- wherein responsive to a potential being applied to an input node, the integrated circuit conveys a current from the input node to an output node of the integrated circuit through the first cell.
A system comprising:
- a memory configured to store instructions;
- an integrated circuit configured to execute the stored instructions, wherein the integrated circuit comprises:
- a first pair of transistors with channels of different doping polarities configured to receive a first input signal by each transistor of the first pair of transistors;
- a second pair of transistors with channels of different doping polarities configured to receive two different input signals, wherein a transistor of a first doping polarity of the second pair of transistors has a greater length of a gate region than a transistor of the second doping polarity of the first pair of transistors;
- and
- wherein responsive to a potential being applied to an input node, the integrated circuit conveys a current from the input node to an output node of the integrated circuit through the first cell.
Dependencies are inferred from the claim text.