3D-stacked semiconductor device including middle isolation structure and BSPDN structure
AssigneeSamsung Electronics Co., Ltd.
InventorsKeumseok Park, Seungchan Yun, Kang-Ill Seo
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Abstract
Provided is a semiconductor device which includes: a 1st source/drain region connected to a 1st channel structure which is controlled by a 1st gate structure; a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure which is controlled by a 2nd gate structure; and a middle isolation structure between the 1st gate structure and the 2nd gate structure, wherein the middle isolation structure comprises two or more vertically-stacked semiconductor layers.
Claims20
A semiconductor device comprising:
- a 1st source/drain region connected to a 1st channel structure which is controlled by a 1st gate structure;
- a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure which is controlled by a 2nd gate structure;
- and
- a middle isolation structure between the 1st gate structure and the 2nd gate structure,
- wherein the middle isolation structure comprises two or more semiconductor layers which are vertically stacked,
- wherein at least one of a portion of the 1st gate structure and a portion of the 2nd gate structure is disposed between the two or more semiconductor layers, and
- wherein the at least one of the portion of the 1st gate structure and the portion of the 2nd gate structure comprises a conductive material that is not electrically connected to a remaining portion of the 1st gate structure or a remaining portion of the 2nd gate structure.
A semiconductor device comprising:
- 1st source/drain regions connected to a 1st channel structure surrounded by a 1st gate structure;
- 2nd source/drain regions, respectively above the 1st source/drain regions, connected to a 2nd channel structure which is surrounded by a 2nd gate structure;
- and
- a middle isolation structure between the 1st gate structure and the 2nd gate structure,
- wherein the middle isolation structure comprises at least one of a portion of the 1st gate structure and a portion of the 2nd gate structure,
- wherein the at least one of the portion of the 1st gate structure and the portion of the 2nd gate structure comprises a conductive material that is not electrically connected to a remaining portion of the 1st gate structure or a remaining portion of the 2nd gate structure, and
- wherein the middle isolation structure comprises at least one semiconductor layer comprising silicon germanium (SiGe) with Ge concentration of 10-15%.
A semiconductor device comprising:
- a 1st source/drain region connected to a 1st channel structure surrounded by a 1st gate structure;
- a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure which is surrounded by a 2nd gate structure;
- and
- a middle isolation structure between the 1st gate structure and the 2nd gate structure,
- wherein the middle isolation structure comprises at least one of a portion of the 1st gate structure and a portion of the 2nd gate structure, and
- wherein the at least one of the portion of the 1st gate structure and the portion of the 2nd gate structure comprises a conductive material that is not electrically connected to a remaining portion of the 1st gate structure or a remaining portion of the 2nd gate structure.
Dependencies are inferred from the claim text.