Thyristor based on charge plasma and cross-point memory array including the same

A thyristor-based cross-point memory array, comprising:

• a plurality of word lines arranged parallel to a first direction;
• a plurality of bit lines arranged parallel to a second direction intersecting the first direction;
• and
• a plurality of memory cells formed in regions where the word lines and the bit lines intersect,
• wherein each of the memory cells comprises a thyristor having a vertical structure, the thyristor comprising a semiconductor core with an insulating film formed on an outer peripheral surface thereof, and a plurality of metal layers formed on the insulating film,
• wherein the semiconductor core includes:
• a first emitter layer formed in a first region corresponding to a first metal layer among the plurality of metal layers based on a charge plasma phenomenon due to a difference in work function with the plurality of metal layers;
• a first base layer formed in a second region corresponding to a second metal layer among the plurality of metal layers based on the charge plasma phenomenon due to the difference in work function with the plurality of metal layers;
• a second base layer formed in a third region corresponding to a third metal layer among the plurality of metal layers based on the charge plasma phenomenon due to the difference in work function with the plurality of metal layers;
• and
• a second emitter layer formed in a region corresponding to a fourth metal layer among the plurality of metal layers based on the charge plasma phenomenon due to the difference in work function with the plurality of metal layers, and
• wherein the second metal layer is formed of a metal having a work function greater than a work function of the third metal layer, thereby increasing a latch-down voltage and a latch-up voltage.