Semiconductor device and manufacturing method thereof

A semiconductor device, comprising:

• a semiconductor substrate;
• a first device, comprising:
• a first channel region over the semiconductor substrate;
• and
• a first gate structure wrapping around the first channel region;
• a second device, comprising:
• a second channel region over the semiconductor substrate;
• and
• a second gate structure wrapping around the second channel region;
• a shallow trench isolation (STI) region between the first channel region and the second channel region;
• a composite isolation structure separating the first gate structure and the second gate structure, comprising:
• a first dielectric layer;
• a second dielectric layer wrapping around the first dielectric layer, wherein the second dielectric layer comprises a high-k oxide material;
• and
• wherein the composite isolation structure extends into the semiconductor substrate below the STI region forming a step structure at a bottom surface of the STI region including a larger width at the bottom surface of the STI region than in the semiconductor substrate.

A manufacturing method of a semiconductor device, comprising:

• providing a semiconductor substrate having fin structures thereon, wherein each fin structure comprises a channel region;
• forming a shallow trench isolation (STI) region between the fin structures;
• forming a dummy gate structure across the fin structures;
• removing a portion of the dummy gate structure, the fin structure directly underneath the portion of the dummy gate structure, and a portion of the semiconductor substrate to form a first opening;
• and
• forming a composite isolation structure in the first opening, comprising:
• forming a first dielectric layer partially covering sidewalls of the first opening, wherein a topmost surface of the first dielectric layer is lower than bottom surfaces of the channel regions;
• forming a second dielectric layer on the first dielectric layer;
• and
• wherein the composite isolation structure extends into the semiconductor substrate below the STI region forming a step structure at a bottom surface of the STI region including a larger width at the bottom surface of the STI region than in the semiconductor substrate.