Wrap around backside source/drain contact
AssigneeInternational Business Machines Corporation
InventorsAnna Lin, Gopal Sankar Kenath, Tao Li, Ruilong Xie
Life of this patent
Estimating the term…
Abstract
Embodiments of the present invention are directed to processing methods and resulting structures for providing wrap-around backside source/drain contacts through a wafer backside. In a non-limiting embodiment, a first field effect transistor and a second filed effect transistor are formed. The first field effect transistor includes a first source or drain (S/D) region, a second S/D region, and a backside contact. The backside contact includes a lower portion and a wrap-around portion wrapping around a lower portion of the second S/D region. The second field effect transistor includes a frontside contact on a S/D region and a backside sacrificial region below the S/D region.
Claims18
A method for forming a semiconductor device, the method comprising:
- forming a first field effect transistor comprising a first source or drain (S/D) region, a second S/D region, and a backside contact, the backside contact comprising a lower portion and a wrap-around portion wrapping around a lower portion of the second S/D region;
- and
- forming a second field effect transistor comprising a frontside contact on a S/D region and a backside sacrificial region below the S/D region;
- wherein the backside sacrificial region below the S/D region in the second field effect transistor is between opposite sidewalls of a shallow trench isolation (STI) liner.
A semiconductor device comprising:
- a first field effect transistor comprising a first source or drain (S/D) region, a second S/D region, and a backside contact, the backside contact comprising a lower portion and a wrap-around portion wrapping around a lower portion of the second S/D region;
- and
- a second field effect transistor comprising a frontside contact on a S/D region and a backside sacrificial region below the S/D region;
- wherein the backside sacrificial region below the S/D region in the second field effect transistor is between opposite sidewalls of a shallow trench isolation (STI) liner.
Dependencies are inferred from the claim text.