MOSFET and memory cell having improved drain current through back bias application

A method of increasing efficiency of write and forming operations of a resistive change element, said method comprising:

• providing a semiconductor device connected to said resistive change element, wherein the resistivity of said resistive change element determines the state of a memory cell, wherein said semiconductor device comprises a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;
• a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type;
• a body having said first conductivity type;
• a source region and a drain region each having said second conductivity type and being separated by said body;
• and a gate positioned in between said source region and said drain region;
• and
• applying an intermediate high voltage to said buried layer to operate said semiconductor device as a transistor with increased on-state drain current, said transistor with increased on-state current being formed by said source region, said gate and said drain region,
• wherein said intermediate high voltage is higher than a relatively low voltage to operate said semiconductor device as an ordinary transistor formed by said source region, said gate and said drain region, and
• wherein said intermediate high voltage is lower than a relatively high voltage to operate said semiconductor device as said semiconductor memory device, wherein said semiconductor memory device has at least two stable states.