3D-stacked semiconductor device having different channel and gate dimensions across lower stack and upper stack

A multi-stack semiconductor device comprising:

• a substrate;
• a lower-stack nanosheet transistor comprising two or more lower channel layers surrounded by a lower gate structure, the lower channel layers connecting lower source/drain regions;
• and
• an upper-stack nanosheet transistor formed above the lower-stack nanosheet transistor, and comprising two or more upper channel layers surrounded by an upper gate structure, the upper channel layers connecting upper source/drain regions,
• wherein at least one of the lower channel layers and at least one of the upper channel layers have different thicknesses,
• wherein the upper gate structure between two adjacent upper channel layers and the lower gate structure between two adjacent lower channel layers have different thicknesses, and
• wherein a thickness of the lower-stack nanosheet transistor is different from a thickness of the upper-stack nanosheet transistor.

A multi-stack semiconductor device comprising:

• a substrate;
• a lower-stack nanosheet transistor comprising two or more lower channel layers surrounded by a lower gate structure, the lower channel layers connecting lower source/drain regions;
• and
• an upper-stack nanosheet transistor formed above the lower-stack nanosheet transistor, and comprising two or more upper channel layers surrounded by an upper gate structure, the upper channel layers connecting upper source/drain regions,
• wherein the lower-stack nanosheet transistor and the upper-stack nanosheet transistor have at least one of:
• a difference between a thickness of one of the lower channel layers and a thickness of one of the upper channel layers;
• and
• a difference between a thickness of the lower gate structure between two adjacent lower channel layers and a thickness of the upper gate structure between two adjacent upper channel layers, and
• wherein a thickness of the lower-stack nanosheet transistor is different from a thickness of the upper-stack nanosheet transistor.