Stepwise internal spacers for stacked transistor structures

An integrated circuit comprising:

• a first semiconductor nanoribbon extending along a first direction between a first source region and a first drain region;
• a second semiconductor nanoribbon extending along the first direction between a second source region and a second drain region, the second semiconductor nanoribbon spaced above the first semiconductor nanoribbon in a second direction different from the first direction;
• a first spacer structure having a first portion extending in the second direction along a side of the first source region, a second portion extending in the second direction along a side of the second source region, and a third portion connecting the first and second portions of the first spacer structure, each of the first, second, and third portions of the first spacer structure being a same continuous material;
• and
• a second spacer structure having a first portion extending in the second direction along a side of the first drain region, a second portion extending in the second direction along a side of the second drain region, and a third portion connecting the first and second portions of the second spacer structure, each of the first, second, and third portions of the second spacer structure being a same continuous material;
• wherein a maximum distance along the first direction between the third portion of the first spacer structure and the third portion of the second spacer structure is more than 5 nm longer than a maximum distance along the first direction between the first portion of the first spacer structure and the first portion of the second spacer structure, and
• wherein the third portion of the first spacer structure outwardly protrudes from the first and second portions of the first spacer structure, and the third portion of the second spacer structure outwardly protrudes from the first and second portions of the second spacer structure.

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a semiconductor device having a first plurality of semiconductor nanoribbons extending in a first direction between a first source region and a first drain region and a second plurality of semiconductor nanoribbons extending in the first direction between a second source region and a second drain region, the first plurality of semiconductor nanoribbons spaced from the second plurality of semiconductor nanoribbons in a second direction orthogonal to the first direction;
• a gate structure around both the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons;
• a first outwardly protruding spacer structure having a first portion extending in the second direction along a side of the first source region, a second portion extending in the second direction along a side of the second source region, and a third portion connecting, and laterally outward from, the first and second portions of the first spacer structure, each of the first, second, and third portions of the first spacer structure being a same continuous material;
• and
• a second outwardly protruding spacer structure having a first portion extending in the second direction along a side of the first drain region, a second portion extending in the second direction along a side of the second drain region, and a third portion connecting, and laterally outward from, the first and second portions of the second spacer structure, each of the first, second, and third portions of the second spacer structure being a same continuous material;
• wherein a maximum distance along the first direction between the third portion of the first spacer structure and the third portion of the second spacer structure is more than 5 nm longer than a maximum distance along the first direction between the first portion of the first spacer structure and the first portion of the second spacer structure.