High electron mobility transistor with helping gate

A method of forming an integrated device, comprising:

• forming a channel layer over a substrate;
• forming a barrier layer over the channel layer;
• removing portions of the barrier layer and the channel layer surrounding a first region of the channel layer, thereby forming a trench within the channel layer surrounding the first region;
• filling the trench with an insulative material;
• forming a semiconductor layer over the first region and the insulative material;
• patterning the semiconductor layer into a semiconductor capping structure with a ring shape from a top-down perspective, wherein the ring shape has a first opening;
• forming a first source/drain electrode within the first opening of the ring shape and on the first region;
• forming a second source/drain electrode outside of the ring shape and on the first region;
• forming a first helping gate on the semiconductor capping structure and localized over a first portion of the ring shape that overlies the insulative material;
• and
• forming a first gate on the semiconductor capping structure and localized over a second portion of the ring shape that overlies the first region.

A method of forming an integrated device, comprising:

• forming a heterojunction structure over a substrate;
• forming an isolation structure around a first region of the heterojunction structure;
• forming a semiconductor capping layer over the heterojunction structure, wherein the semiconductor capping layer comprises a first portion overlying the heterojunction structure and a second portion overlying the isolation structure;
• forming a first source/drain electrode on a first side of the semiconductor capping layer;
• forming a second source/drain electrode on a second side of the semiconductor capping layer, wherein the second source/drain electrode is separated from the first source/drain electrode in a first direction by the semiconductor capping layer;
• forming a first helping gate on the second portion of the semiconductor capping structure, wherein the first helping gate is spaced from the first region in a second direction transverse to the first direction;
• forming a first gate dielectric over the semiconductor capping layer after forming the first helping gate;
• and
• forming a first gate on the first portion of the semiconductor capping structure and between the first source/drain electrode and the second source/drain electrode, wherein the first gate is formed after forming the first gate dielectric, wherein the first gate is separated from the first helping gate in the first direction and the second direction, and wherein the first gate is separated from the semiconductor capping structure by the first gate dielectric.