Semiconductor device

A semiconductor device comprising:

• a peripheral circuit structure;
• and
• a cell structure stacked on the peripheral circuit structure,
• wherein the cell structure comprises:
• a plurality of gate electrodes, each of the gate electrodes being spaced apart from each other in a vertical direction;
• a channel structure passing through the plurality of gate electrodes and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end;
• and
• a common source layer disposed above the plurality of gate electrodes and covering the second end of the channel structure,
• wherein the common source layer comprises:
• a plurality of first regions, each first region being of a first conductivity type and extending in a first horizontal direction;
• and
• a plurality of second regions, each second region being of a second conductivity type different from the first conductivity type and extending in the first horizontal direction,
• wherein the first regions and the second regions are alternately arranged in a second horizontal direction crossing the first horizontal direction.

A semiconductor device comprising:

• a peripheral circuit structure;
• and
• a cell structure stacked on the peripheral circuit structure and comprising a cell region, a connection region, and a peripheral circuit connection region,
• wherein the cell structure comprises:
• a plurality of gate electrodes, each of the gate electrodes being arranged in the cell region and spaced apart from each other in a vertical direction;
• a channel structure passing through the plurality of gate electrodes in the cell region and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end;
• a pad portion having a step shape and extending from the plurality of gate electrodes in the connection region;
• a first plug connected to the pad portion, passing through the pad portion, and extending in the vertical direction;
• a stack insulating layer surrounding the plurality of gate electrodes in a plan view;
• a second plug passing through the stack insulating layer in the peripheral circuit connection region and extending in the vertical direction;
• and
• a common source layer located in the cell region and covering the second end of the channel structure,
• wherein the channel structure comprises a channel layer extending in the vertical direction,
• wherein the common source layer comprises a first region and a second region that contain impurities of different conductivity types, and
• wherein the first region of the common source layer comprises a P-type conductivity and is connected to at least a portion of the channel layer.