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US 12,757,433 B2Granted
Semiconductor device structure with butted-contact and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Chiang Tsai, Jeng-Ya Yeh, Mu-Chi Chiang
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Abstract
Embodiments of the present disclosure relates to a semiconductor device structure. The structure includes a first source/drain feature, a first interlayer dielectric (ILD) disposed over the first source/drain feature, a first conductive feature extending through the first ILD and in electrical contact with the first source/drain feature, and a gate electrode layer extending through the first ILD and disposed adjacent the first conductive feature, wherein a top surface of the first conductive feature and a top surface of the gate electrode layer are substantially co-planar.
Claims20
A method for forming a semiconductor device structure, comprising:
- providing first and second source/drain features on opposing sides of a gate structure;
- forming a first interlayer dielectric (ILD) over the first and second source/drain features;
- removing portions of the first ILD to form first and second contact openings, wherein the first contact opening has an L-shaped profile that exposes a portion of the first source/drain feature and a portion of a gate dielectric of the gate structure, and the second contact opening is extended to expose a portion of the second source/drain feature;
- filling the first and second contact openings with a conductive material to form first and second conductive features, respectively, wherein the first conductive feature has a first portion in lateral contact with the gate dielectric and a second portion overlying the first source/drain feature;
- performing a planarization process so that top surfaces of the gate structure, the first conductive feature, and the second conductive feature are substantially co-planar;
- forming a second ILD over the first ILD;
- removing portions of the second ILD to form a butted contact opening exposing the top surfaces of the first conductive feature and the gate structure;
- and
- filling the butted contact opening with one or more conductive materials to form a butted contact.
6 more elements
A method of forming a semiconductor device structure, comprising:
- forming a plurality of gate structures over a substrate;
- forming a first contact etch stop layer and a first interlayer dielectric over the substrate and the gate structures;
- forming contact openings through the first interlayer dielectric and the first contact etch stop layer to expose source/drain features, wherein the contact openings have an L-shaped profile that exposes a portion of the source/drain features and a portion of a gate dielectric of at least one gate structure;
- filling the contact openings with a conductive material to form conductive features, wherein each conductive feature has a first portion in lateral contact with the gate dielectric and a second portion overlying the source/drain feature;
- forming a third interlayer dielectric over the conductive features and the gate structures;
- etching the third interlayer dielectric to form butted contact openings that concurrently expose a top surface of at least one conductive feature and a top surface of a gate electrode, wherein the butted contact openings are formed from an L-shaped opening defined by a single lithography and etching process;
- and
- forming a butted contact in the butted contact opening to electrically connect the conductive feature with the gate electrode.
5 more elements
A method of manufacturing a semiconductor device structure, comprising:
- forming a plurality of transistors each having a gate structure and a source/drain feature;
- forming a first dielectric stack comprising a contact etch-stop layer and a first interlayer dielectric over the transistors;
- etching the first dielectric stack to form L-shaped openings exposing portions of the source/drain features and a portion of a gate dielectric of an adjacent gate structure;
- forming conductive features in the L-shaped openings such that each conductive feature comprises a first portion in lateral contact with the gate dielectric adjacent the gate structure and a second portion overlying the source/drain feature;
- planarizing the conductive features and the first dielectric stack until top surfaces of the conductive features and gate electrodes are coplanar;
- forming a second dielectric stack over the planarized structure;
- etching the second dielectric stack to form butted-contact openings exposing both the top surfaces of the conductive features and the top surfaces of the gate electrodes;
- and
- filling the butted-contact openings with a conductive material to form butted contacts electrically coupling the conductive features and the gate electrodes.
6 more elements
Dependencies are inferred from the claim text.