Enhancement-mode HEMT and manufacturing process of the same

A manufacturing process of an enhancement mode high-electron-mobility transistor (HEMT) device, the process comprising:

• forming a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas, 2DEG;
• and
• forming, on the top surface of the semiconductor body, a gate structure biasable to electrically control the 2DEG and including a functional layer and a gate contact in direct physical and electrical contact with each other, wherein the gate contact is of conductive material and the functional layer is of two-dimensional semiconductor material and includes a first doped portion with P-type electrical conductivity on the top surface of the semiconductor body interposed between the semiconductor body and the gate contact along a first axis, wherein the gate contact includes a first gate contact and a second gate contact spaced apart from each other on the two-dimension semiconductor material in a first direction;
• and
• forming a source contact and a drain contact each of conductive material and on the top surface of the semiconductor body and spaced apart from each other in a second direction orthogonal to the first direction, wherein the first and second gate contacts are spaced apart in the first direction by a distance larger than a width of the source contact and the drain contact in the first direction, wherein the source contact and the drain contact are spaced apart from each other in the second direction by a distance greater than a width of the first and second gate contacts in the second direction.

A method, comprising:

• forming a heterostructure of an enhancement mode high-electron-mobility transistor (HEMT) device, the heterostructure including a channel layer and a barrier layer on the channel layer;
• forming a functional layer of a gate structure of the HEMT device on the barrier layer by depositing a two dimensional semiconductor material on the barrier layer;
• forming a gate contact of the gate structure on the functional layer, wherein the functional layer has a first portion directly below the gate contact and a second portion that is not directly below the gate contact;
• and
• forming a source contact and a drain contact of the HEMT device on the barrier layer and spaced apart from the functional layer, wherein the gate contact includes a first gate contact and a second gate contact spaced apart from each other on the two-dimension semiconductor material in a first direction, wherein the source contact and the drain contact spaced apart from each other in a second direction orthogonal to the first direction, wherein the first and second gate contacts are spaced apart in the first direction by a distance larger than a width of the source contact and the drain contact in the first direction, wherein the source contact and the drain contact are spaced apart from each other in the second direction by a distance greater than a width of the first and second gate contacts in the second direction.