Method of fabricating transistors with implanting dopants at first and second dosages in the collector region to form the base region

A method of forming an integrated circuit, comprising:

• forming a first doped region having a first conductivity type extending into a semiconductor substrate and having a first contact region extending to a top surface of the semiconductor substrate;
• forming a second doped region having an opposite second conductivity type within the first doped region and having a second contact region that extends to the top surface of the semiconductor substrate, the second doped region laterally surrounded by the first contact region;
• forming a third doped region having the first conductivity type within and laterally surrounded by the second doped region;
• forming a polysilicon structure on an oxide layer over the second doped region, the polysilicon structure and the oxide layer having an interior sidewall, the interior sidewall defining a boundary of the third doped region;
• forming a sidewall dielectric layer on the interior sidewall, the sidewall dielectric layer extending over the third doped region and a top surface of the polysilicon structure;
• and
• forming a silicide layer on a silicided portion of the third doped region spaced apart from the second doped region by the sidewall dielectric layer and laterally surrounded at a surface of the semiconductor substrate by an unsilicided portion of the third doped region.

A method of forming a bipolar junction transistor of an integrated circuit, comprising:

• forming a collector region having majority carriers of a first type extending into a semiconductor substrate, the collector region including a collector contact that intersects a top surface of the semiconductor substrate;
• forming a base region having majority carriers of an opposite second opposite type between the collector region and a surface of the substrate, the base region including a base contact that intersects the top surface of the semiconductor substrate and is surrounded by the collector contact;
• forming an emitter region having majority carriers of the first type between the base region and the surface of the semiconductor substrate, the emitter region laterally surrounded by the base region and the base contact;
• forming a gate dielectric ring over the base region, the gate dielectric ring having an interior sidewall, the interior sidewall defining a boundary of the emitter region;
• forming a sidewall spacer layer on the interior sidewall, the sidewall spacer layer extending over the emitter region and a top surface of the gate dielectric ring;
• and
• forming a silicide layer over the emitter region and spaced apart from the base region and laterally surrounded at the surface of the substrate by the emitter region.