Replacement electrode process for 3D ferroelectric memory

A method, comprising:

• forming an opening in an interleaved stack of insulator layers and sacrificial layers;
• exposing a portion of each of the insulator layers adjacent to the opening by recessing a sidewall of the sacrificial layers between the insulator layers;
• forming an inner plate in contact with the exposed portion of each of the insulator layers by at least partially filling the opening with a conductive material;
• exposing a sidewall of the inner plate by removing each of the sacrificial layers from between the insulator layers;
• forming ferroelectric material on the exposed sidewall of the inner plate and in contact with the insulator layers;
• and
• forming a plurality of ferroelectric capacitors by forming outer plates over the ferroelectric material, wherein each of the outer plates is between two of the insulator layers.

An integrated circuit (IC) device, comprising:

• a capacitor stack, comprising:
• a first plate;
• a stack of second plates, wherein the first plate extends through the stack of second plates;
• a ferroelectric layer between the first plate and each of the second plates, wherein the ferroelectric layer is in contact with the first plate, and wherein the first plate, individual ones of the second plates, and the ferroelectric layer form a plurality of ferroelectric capacitors;
• and
• a first insulator layer above each of the second plates and a second insulator layer below each of the second plates, wherein an interface material is between the first plate and each of the first insulator layers and between the first plate and each of the second insulator layers;
• a plurality of platelines, each of the platelines connected to a corresponding one of the second plates;
• and
• a select transistor coupled to the first plate.

A method, comprising:

• forming an opening in an interleaved stack of insulator layers and sacrificial layers;
• forming an etch-stop layer over a sidewall of the opening;
• forming an inner plate over the etch-stop layer and at least partially filling the opening;
• exposing sidewall portions of the etch-stop layer that are between the insulator layers by removing the sacrificial layers;
• removing the exposed sidewall portions of the etch-stop layer while retaining sidewall portions of the etch-stop layer that are between the inner plate and the insulator layers;
• forming ferroelectric material between the insulator layers;
• forming a plurality of ferroelectric capacitors by forming outer plates by depositing metal between the insulator layers;
• forming a plurality of platelines, each of the platelines connected to an individual one of the outer plates;
• and
• forming a select transistor coupled to the inner plate.