Highly integrated semiconductor device

A semiconductor device comprising:

• a first cell array on a substrate, the first cell array comprising:
• a first bit line and a first source line spaced apart from each other in a first direction parallel to an upper surface of the substrate;
• a first gate electrode between the first bit line and the first source line, wherein the first gate electrode extends in a second direction perpendicular to the upper surface of the substrate;
• and
• first channel patterns on a side surface of the first gate electrode and spaced apart from each other in the second direction;
• a first bit line pad electrically connected to the first bit line;
• and
• a first source line pad electrically connected to the first source line,
• wherein the first bit line and the first source line extend in a third direction parallel to the upper surface of the substrate and intersecting the first direction,
• wherein the first bit line pad is offset from the first source line pad in both the first direction and the third direction with the first cell array therebetween, and
• wherein the first bit line pad and the first bit line form a first L-shape, the first source line pad and the first source line form a second L-shape, and the first L-shape and the second L-shape are rotationally symmetric.

A semiconductor device comprising:

• a first cell array and a second cell array on a substrate and adjacent to each other in a first direction parallel to an upper surface of the substrate,
• the first cell array comprising:
• a first gate electrode that extends in a second direction perpendicular to the upper surface of the substrate;
• first channel patterns on a side surface of the first gate electrode and spaced apart from each other in the second direction;
• and
• first conductive lines respectively electrically connected to the first channel patterns and spaced apart from each other in the second direction, and
• the second cell array comprising:
• a second gate electrode that extends in the second direction;
• second channel patterns on a side surface of the second gate electrode and spaced apart from each other in the second direction;
• and
• second conductive lines respectively electrically connected to the second channel patterns and spaced apart from each other in the second direction;
• first conductive line pads respectively electrically connected to the first conductive lines;
• and
• second conductive line pads respectively electrically connected to the second conductive lines,
• wherein the first conductive line pads are offset from the second conductive line pads in both the first direction and a third direction which is parallel to the upper surface of the substrate and intersects the first direction, with the first and second cell arrays therebetween, and
• wherein the first conductive line pads and/or the second conductive line pads are stacked in the second direction in a stepped structure.