Three-dimensional semiconductor memory device, electronic system including the same, and method of fabricating the same

A three-dimensional semiconductor memory device, comprising:

• a peripheral circuit structure on a first substrate;
• a cell array structure on the peripheral circuit structure;
• and
• a backside structure on the cell array structure,
• wherein the cell array structure includes:
• a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked along a first direction;
• a source structure on the stack structure;
• a vertical structure that extends in the first direction through the stack structure and is electrically connected to the source structure;
• a through plug that extends in the first direction through the stack structure, the through plug including a first surface adjacent to the backside structure and a second surface opposite to the first surface;
• a middle circuit structure between the stack structure and the peripheral circuit structure, the middle circuit structure being electrically connected to the peripheral circuit structure;
• and
• a connection plug electrically connected to the middle circuit structure and the backside structure,
• wherein the backside structure includes:
• a second substrate on the source structure;
• backside contact plugs electrically connected to the through plug and the connection plug, respectively, at least a portion of the backside contact plugs extending in the second substrate;
• and
• a backside contact line that electrically connects the backside contact plugs to each other,
• wherein the through plug is electrically connected through the first surface to the backside structure and the connection plug, and
• wherein the first surface is higher in the first direction than a top surface of an uppermost one of the interlayer dielectric layers with the first substrate providing a base reference plane.

An electronic system, comprising:

• a three-dimensional semiconductor memory device including a peripheral circuit structure, a cell array structure, and a backside structure that are stacked on a first substrate;
• and
• a controller that is electrically connected through an input/output pad to the three-dimensional semiconductor memory device and is configured to control the three-dimensional semiconductor memory device,
• wherein the cell array structure includes:
• a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked along a first direction;
• through plugs that extend in the first direction through the stack structure, each of the through plugs including a first surface adjacent to the backside structure and a second surface opposite to the first surface;
• a middle circuit structure between the stack structure and the peripheral circuit structure, the middle circuit structure being electrically connected to the peripheral circuit structure;
• and
• a connection plug electrically connected to the middle circuit structure and the backside structure,
• wherein the through plugs include a first through plug that is electrically connected through the first surface to the backside structure and a second through plug that is electrically connected through the second surface to the middle circuit structure, and at least one of (i) the first through plug is electrically connected to a first pad portion of a first gate electrode of the gate electrodes or (ii) the second through plug is electrically connected to a second pad portion of a second gate electrode of the gate electrodes.