Semiconductor device including active pattern on bitline

A semiconductor device comprising:

• a substrate;
• a plurality of bitlines extending in a first direction on the substrate, and spaced apart from each other in a second direction perpendicular to the first direction;
• a plurality of first active patterns and a plurality of second active patterns on the plurality of bit-lines, the plurality of second active patterns corresponding to the plurality of first active patterns;
• a back gate electrode arranged between one of the plurality of first active patterns and one of the plurality of second active patterns, and extending in the second direction across the plurality of bitlines;
• a first wordline extending in the direction beside adjacent to respective sides of the plurality of first active patterns;
• and
• a second wordline extending in the second direction adjacent to respective sides of the plurality of second active patterns, and spaced apart from the first wordline in the first direction,
• wherein:
• each of the first active patterns, the back gate electrode, and each of the second active patterns are located between the first wordline and the second wordline, and
• a length of each of the first active patterns and a length of each of the second active patterns in the second direction are each greater than a length of each of the plurality of bitlines in the second direction.

A semiconductor device comprising:

• a substrate;
• a plurality of bitlines extending in a first direction on the substrate, and spaced apart from each other in a second direction perpendicular to the first direction;
• a plurality of first active patterns on the plurality of bitlines;
• a plurality of second active patterns on the plurality of bitlines;
• a plurality of back gate electrodes arranged between the plurality of first active patterns and the plurality of second active patterns, and extending in the second direction across the plurality of bit-lines;
• a first wordline extending in the second direction adjacent to one side of one of the plurality of first active patterns;
• and
• a second wordline extending in the second direction adjacent to one side of one of the plurality of second active patterns, the second wordline spaced apart from the first wordline in the first direction,
• wherein:
• one of the plurality of first active patterns, one of the plurality of back gate electrodes, and one of the plurality of second active patterns are located between the first and second wordlines,
• the plurality of first active patterns includes first surfaces facing one of the plurality of back gate electrodes and second surfaces facing the first wordline,
• the plurality of second active patterns includes first surfaces facing the one of the plurality of back gate electrodes and second surfaces facing the second wordline,
• each of the second surfaces of the plurality of first active patterns includes a portion rounded toward both ends of the respective second surface in the second direction so as to be gradually closer to the one of the plurality of back gate electrodes,
• each of the second surfaces of the plurality of second active patterns includes a portion rounded toward both ends of the respective second surface in the second direction so as to be gradually closer to the one of the plurality of back gate electrodes,
• the first wordline includes a first protrusion located between adjacent first active patterns of the plurality of first active patterns, and
• the second wordline includes a second protrusion located between adjacent second active patterns of the plurality of second active patterns.