US 12,757,378 B2 · Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate including a memory cell region, a first bit line on a center region of the memory cell region, a first landing pad on the first bit line, a first bit line capping pattern between the first bit line and first landing pad, a second bit line on an edge region of the memory cell region, a second landing pad on the second bit line, and a second bit line capping pattern between the second bit line and the second landing pad. The first and second bit line capping patterns vertically overlap the first and second landing pads, respectively. A distance from the top of the first bit line capping pattern from the top of the first landing pad is greater than a distance from the top of the second bit line capping pattern to from the top of the second landing pad.

Claims20

Dependent claims

A semiconductor memory device comprising:

a substrate including a memory cell region, the memory cell region including a cell center region and a cell edge region surrounding the cell center region;
a first bit line on the cell center region;
a first landing pad on the first bit line;
a first bit line capping pattern between the first bit line and the first landing pad;
a second bit line on the cell edge region;
a second landing pad on the second bit line;
and
a second bit line capping pattern between the second bit line and the second landing pad, wherein
the first bit line capping pattern vertically overlaps the first landing pad,
the second bit line capping pattern vertically overlaps the second landing pad, and
a first distance from an upper surface of the first bit line capping pattern to an upper surface of the first landing pad is greater than a second distance from an upper surface of the second bit line capping pattern to an upper surface of the second landing pad.

8 more elements

A semiconductor memory device comprising:

a substrate including a memory cell region, the memory cell region including a cell center region and a cell edge region surrounding the cell center region;
a first bit line on the cell center region;
a first landing pad on the first bit line;
a first bit line capping pattern between the first bit line and the first landing pad;
a second bit line on the cell edge region;
a second landing pad on the second bit line;
and
a second bit line capping pattern between the second bit line and the second landing pad, wherein
the first landing pad includes a first lower metal pattern and a first upper metal pattern on the first lower metal pattern,
the second landing pad includes a second lower metal pattern and a second upper metal pattern on the second lower metal pattern,
an upper portion of the first lower metal pattern vertically overlaps the first bit line capping pattern,
an upper portion of the second lower metal pattern vertically overlaps the second bit line capping pattern, and
a first thickness of the upper portion of the first lower metal pattern is greater than a second thickness of the upper portion of the second lower metal pattern.

10 more elements

A semiconductor memory device comprising:

a substrate including a memory cell region, a peripheral region, and a boundary region, the memory cell region including a cell center region and a cell edge region surrounding the cell center region, the peripheral region surrounding the memory cell region, and the boundary region being between the peripheral region and the cell edge region;
a first bit line on the cell center region;
a first landing pad on the first bit line, the first landing pad including a first lower metal pattern and a first upper metal pattern on the first lower metal pattern;
a first bit line capping pattern between the first bit line and the first landing pad;
a second bit line on the cell edge region;
a second landing pad on the second bit line, the second landing pad including a second lower metal pattern and a second upper metal pattern on the second lower metal pattern;
a second bit line capping pattern between the second bit line and the second landing pad;
a dummy metal-containing pattern on the boundary region;
a dummy capping pattern on the dummy metal-containing pattern;
a third lower metal pattern on a side surface of the dummy capping pattern;
and
a third upper metal pattern on an upper surface of the dummy capping pattern, wherein
the first upper metal pattern, the second upper metal pattern, and the third upper metal pattern include a same metal material,
the first upper metal pattern is vertically spaced apart from the first bit line capping pattern with the first lower metal pattern interposed therebetween,
the second upper metal pattern is vertically spaced apart from the second bit line capping pattern with the second lower metal pattern interposed therebetween, and
the third upper metal pattern is in contact with the dummy capping pattern.

13 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20