Memory device having improved P—N junction and manufacturing method thereof

A memory device, comprising:

• a semiconductor substrate defined with a first active area and a second active area;
• a gate structure adjacent to the first and second active areas and indented into the semiconductor substrate from a first surface of the semiconductor substrate;
• a doped member extending into the semiconductor substrate and surrounded by the first active area;
• a conductive layer, including a first portion extending into the semiconductor substrate from the first surface of the semiconductor substrate and a second portion disposed over the doped member and coupled to the first portion;
• a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the first active area of the semiconductor substrate, and a second insulating layer disposed over the gate structure, wherein the first insulating layer and the second insulating layer are separated from each other;
• a first contact and a second contact surrounded by a first dielectric layer, wherein the first contact is disposed on the first portion and the second portion of the conductive layer, wherein the second contact is disposed over the second active region;
• and
• a first conductive pillar and a second conductive pillar disposed over the first dielectric layer,
• wherein the first portion of the conductive layer is disposed between the gate structure and the doped member;
• wherein the second portion of the conductive layer is disposed over the first active area and the second insulating layer is disposed over the second active area.