Memory device including capacitor contacts having different materials and method for preparing the same
AssigneeNanya Technology Corporation
InventorYing-Cheng Chuang
Life of this patent
Estimating the term…
Abstract
A memory device includes a bit line structure disposed over a semiconductor substrate, and a lower capacitor contact disposed in and extending above the semiconductor substrate. The lower capacitor contact includes polysilicon. The memory device also includes an upper capacitor contact disposed over the lower capacitor contact. The upper capacitor contact includes titanium nitride. The memory device further includes a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the upper capacitor contact and the bit line structure. In addition, the memory device includes a capacitor disposed over the first spacer layer.
Claims16
A memory device, comprising:
- a bit line structure disposed over a semiconductor substrate;
- a lower capacitor contact disposed in and extending above the semiconductor substrate, wherein the lower capacitor contact comprises polysilicon;
- an upper capacitor contact disposed over the lower capacitor contact, wherein the upper capacitor contact comprises titanium nitride (TiN);
- a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the upper capacitor contact and the bit line structure;
- a capacitor disposed over the first spacer layer;
- a bit line mask layer disposed over the bit line structure, wherein the capacitor is disposed over and in direct contact with the bit line mask layer;
- and
- a third spacer layer covering the bit line mask layer, wherein the third spacer layer extends to contact the upper capacitor contact;
- wherein a top surface of the bit line mask layer is higher than a top surface of the upper capacitor contact.
A memory device, comprising:
- a bit line structure disposed over a semiconductor substrate;
- a lower capacitor contact disposed in and extending above the semiconductor substrate;
- an upper capacitor contact disposed over the lower capacitor contact, wherein the upper capacitor contact and the lower capacitor contact comprise different materials;
- a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the upper capacitor contact and the bit line structure;
- a capacitor disposed over the first spacer layer;
- and
- a landing pad disposed over the upper capacitor contact and in direct contact with the capacitor;
- wherein a height of the upper capacitor contact is greater than or equal to a height of the lower capacitor contact.
Dependencies are inferred from the claim text.