Vertical transistors with backside power delivery

An apparatus, comprising:

• a first vertical transistor formed in a transistor region of an integrated circuit cell structure, the first vertical transistor having a lower source/drain region, a first gate, and an upper source/drain region stacked in a vertical dimension;
• a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source/drain region, a second gate, and an upper source/drain region stacked in the vertical dimension, the second gate being merged with the first gate, wherein the second vertical transistor is parallel to the first vertical transistor with at least some first spacing in a horizontal dimension between the first and second vertical transistors;
• a third vertical transistor formed in the transistor region of the integrated circuit cell structure, the third vertical transistor having a lower source/drain region, a third gate, and an upper source/drain region stacked in the vertical dimension;
• a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source/drain region, a fourth gate, and an upper source/drain region stacked in the vertical dimension, the fourth gate being merged with the third gate, wherein the fourth vertical transistor is parallel to the third vertical transistor with the at least some first spacing in the horizontal dimension between the third and fourth vertical transistors;
• wherein the second and fourth vertical transistors are a complementary transistor type to the first and third vertical transistors, and wherein the third and fourth vertical transistors are parallel to the first and second vertical transistors with at least some second spacing in the horizontal dimension, the second spacing being perpendicular to the first spacing;
• a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes signal routing;
• a second metal layer located below the transistor region in the vertical dimension, wherein the second metal layer includes power routing;
• a third metal layer positioned below the lower source/drain regions and above the second metal layer, wherein the third metal layer includes:
• a first metal contact coupled to the lower source/drain region of the first vertical transistor;
• a second metal contact coupled to the lower source/drain region of the second vertical transistor;
• and
• a third metal contact coupled to the lower source/drain region of the third vertical transistor;
• a fourth metal layer positioned above the upper source/drain regions and below the first metal layer, wherein the fourth metal layer includes:
• a first metal strap coupled between the upper source/drain region of the first vertical transistor and the upper source/drain region of the third vertical transistor;
• and
• a second metal strap coupled between the upper source/drain region of the second vertical transistor and the upper source/drain region of the fourth vertical transistor;
• a first via coupled between the first metal contact and the power routing in the second metal layer;
• a second via coupled between the second metal contact and the power routing in the second metal layer;
• and
• a third via coupled between the third metal contact and the power routing in the second metal layer.

An apparatus, comprising:

• a first vertical transistor formed in a transistor region of an integrated circuit cell structure, the first vertical transistor having a lower source/drain region, a first gate, and an upper source/drain region stacked in a vertical dimension;
• a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source/drain region, a second gate, and an upper source/drain region stacked in the vertical dimension, wherein the second vertical transistor is parallel to the first vertical transistor with at least some first spacing in a horizontal dimension between the first and second vertical transistors;
• a third vertical transistor formed in the transistor region of the integrated circuit cell structure, the third vertical transistor having a lower source/drain region, a third gate, and an upper source/drain region stacked in the vertical dimension;
• a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source/drain region, a fourth gate, and an upper source/drain region stacked in the vertical dimension, wherein the fourth vertical transistor is parallel to the third vertical transistor with the at least some first spacing in the horizontal dimension between the third and fourth vertical transistors;
• wherein the second and fourth vertical transistors are a complementary transistor type to the first and third vertical transistors, and wherein the third and fourth vertical transistors are parallel to the first and second vertical transistors with at least some second spacing in the horizontal dimension, the second spacing being perpendicular to the first spacing;
• a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes signal routing;
• a third metal layer positioned below the lower source/drain regions, wherein the third metal layer includes:
• a metal contact plate coupled to the lower source/drain regions of the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor;
• a fourth metal layer positioned above the upper source/drain regions and below the first metal layer, wherein the fourth metal layer includes:
• a first metal strap coupled between the upper source/drain region of the first vertical transistor and the upper source/drain region of the second vertical transistor;
• and
• a second metal strap coupled between the upper source/drain region of the third vertical transistor and the upper source/drain region of the fourth vertical transistor.