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US 12,757,319 B2Granted
Substrate structures and methods of manufacture
AssigneeSemiconductor Components Industries, LLC
InventorsYusheng Lin, Roger Paul Stout, Chee Hiong Chew, Sadamichi Takakusaki, Francis J. Carney
Life of this patent
Estimating the term…
Abstract
Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.
Claims15
A semiconductor package, comprising:
- a patterned metallic baseplate comprising a first surface and a second surface opposing the first surface;
- a first laminate insulative layer comprising a first surface coupled to the second surface of the patterned metallic baseplate, the first laminate insulative layer having a second surface opposing the first surface of the first laminate insulative layer;
- a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the second surface of the first laminate insulative layer at a first surface of the metallic trace, each metallic trace of the first plurality of metallic traces having a second surface opposing the first surface of the metallic trace;
- one or more semiconductor devices comprising a first surface and a second surface opposing the first surface, wherein the first surface of the one or more semiconductor devices are coupled to the second surface of each one of the first plurality of metallic traces;
- a second plurality of metallic traces comprising a first surface and a second surface, wherein the first surface of at least one metallic trace of the second plurality of metallic traces is coupled to the second surface of the one or more semiconductor devices;
- and
- a second laminate insulative layer comprising a first surface coupled to the second surfaces of the metallic traces of the second plurality of metallic traces;
- wherein a plurality of thicker portions are directly coupled between the first plurality of traces and the second plurality of traces and one of the plurality of thicker portions is coupled between the semiconductor devices.
5 more elements
A semiconductor package, comprising:
- a patterned metallic baseplate comprising a first surface and a second surface opposing the first surface;
- an electrically insulative layer comprising a first surface coupled to the second surface of the patterned metallic baseplate, the electrically insulative layer having a second surface opposing the first surface of the electrically insulative layer;
- a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the second surface of the electrically insulative layer at a first surface of the metallic trace, each metallic trace of the first plurality of metallic traces having a second surface opposing the first surface of the metallic trace;
- one or more semiconductor devices comprising a first surface and a second surface opposing the first surface, wherein the first surface of the one or more semiconductor devices are coupled to the second surface of each one of the first plurality of metallic traces;
- a second plurality of metallic traces comprising a first surface and a second surface, wherein the first surface of at least one metallic trace of the second plurality of metallic traces is coupled to the second surface of the one or more semiconductor devices;
- a second insulative layer comprising a first surface coupled to the second surfaces of the metallic traces of the upper plurality of metallic traces;
- and
- a mold compound encapsulating the one or more semiconductor devices;
- wherein the semiconductor package is configured to electrically couple to an external device through external connectors directly coupled to the first plurality of metallic traces and not to the second plurality of metallic traces;
- and
- wherein a plurality of thicker portions are directly coupled between the first plurality of traces and the second plurality of traces and one of the plurality of thicker portions is coupled between the semiconductor devices.
8 more elements
Dependencies are inferred from the claim text.