Hierarchical mapping for network on chip

A system comprising a control module, configured to:

• for an input of a hierarchical topology comprising a topology of the NoC as built using multiple instances of different sub-NoC designs arranged in a hierarchy, each of the different sub-NoCs designs comprising routers and bridges interconnected in a predetermined manner, and a flow list comprising traffic or instance flows between any host pair associated with the NoC:
• for each of the different sub-NoC designs in the hierarchical topology, identify hierarchically distinct flows across a plurality of instances of the each of the different sub-NoC designs through grouping, from the flow list, flow instances associated with each of the plurality of instances of the each of the different sub-NoC designs;
• determine a unified route and Virtual Channel (VC) for each of the hierarchically distinct flows;
• and
• project the unified route and VC back to paths through each of the plurality of instances of the each of the different sub-NoC designs.

A non-transitory computer-readable medium storing instructions for mapping flows of a Network on Chip (NoC), the instructions comprising:

• for an input of a hierarchical topology comprising a topology of the NoC as built using multiple instances of different sub-NoC designs arranged in a hierarchy, each of the different sub-NoCs designs comprising routers and bridges interconnected in a predetermined manner, and a flow list comprising traffic or instance flows between any host pair associated with the NoC:
• for each of the different sub-NoC designs in the hierarchical topology, identifying hierarchically distinct flows across a plurality of instances of the each of the different sub-NoC designs through grouping, from the flow list, flow instances associated with each of the plurality of instances of the each of the different sub-NoC designs;
• determining a unified route and Virtual Channel (VC) for each of the hierarchically distinct flows;
• and
• projecting the unified route and VC back to paths through each of the plurality of instances of the each of the different sub-NoC designs.