Phase management circuit for high-speed ADC receivers and methods thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsTamal Das, Gopinath Rayasam, Sanjeeb Kumar Ghosh, Saikat Hazra
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Abstract
Embodiments herein disclose a phase control circuit for a high-speed ADC clock receiver in a PAM4 receiver comprises of, a plurality of Current-Mode Logic (CML) IQ dividers, a plurality of phase interpolators, and a detector circuit, wherein the detector circuit determines phase relation between plurality of clock signals from the plurality of CML IQ dividers and control inputs of the plurality of phase interpolators in a clock data recovery loop based on the determined phase relation.
Claims12
A circuit configured to manage phase for a high-speed analog-to-digital converter (ADC) clock receiver in a pulse-amplitude modulation (PAM) receiver, comprising:
- one or more Current-Mode Logic (CML) in-phase/quadrature (IQ) dividers;
- a plurality of phase interpolators;
- one or more CML to Complementary Metal-Oxide-Semiconductor (CMOS) converters connected to an output of at least one of the plurality of phase interpolator;
- and
- a detector circuit configured to determine a phase relation between a plurality of clock signals received from the one or more CML IQ dividers, and control inputs of the plurality of phase interpolators in a Clock and Data Recovery (CDR) loop based on the determined phase relation.
A method for managing phase for a high-speed clock for an analog-to-digital-converter-digital signal processor (ADC-DSP) based receiver in a pulse-amplitude modulation (PAM) receiver, the method comprising:
- determining, by a detector circuit, a phase relation between a plurality of clock signals received from a plurality of Current-Mode Logic (CML) in-phase/quadrature (IQ) dividers;
- and
- controlling, by the detector circuit, inputs of a plurality of phase interpolators in a Clock and Data Recovery (CDR) loop based on the determined phase relation.
Dependencies are inferred from the claim text.