Integrated circuit for performing link equalization

An integrated circuit comprising:

• a first receiver configured to receive a first signal from an external integrated circuit after an initial link equalization is completed;
• a reception equalizer configured to compensate for signal distortion of the first signal to generate a second signal;
• an eye margin check module configured to:
• measure an eye margin of the second signal,
• compare the measured eye margin with a threshold eye margin to obtain a comparison result, and
• store the comparison result;
• and
• a first transmitter configured to:
• transmit the comparison result to the external integrated circuit as an asynchronous event request (AER), and
• wherein the integrated circuit receives a register read command corresponding to the AER from a second transmitter of the external integrated circuit, transmits the stored comparison result to a second receiver of the external integrated circuit and performs a link re-equalization operation with the external integrated circuit.

A storage device comprising at least one processor configured to:

• perform an initial link equalization with a host;
• measure an eye margin of a signal received from the host during an operation with the host;
• store the measured eye margin and a comparison result determined based on a comparison between the measured eye margin and a threshold eye margin;
• transmit the comparison result to the host based on an asynchronous event request (AER);
• and
• perform a link re-equalization with the host based on the comparison result.