Double-data rate transmission within a system-on-chip via network-on-chip interconnects

A method for transmitting data from a source circuit to a sink circuit using a network-on-chip (NOC) interconnect, wherein the NOC interconnect is clocked using a source synchronous clock signal, the method comprising:

• a local programmable delay circuit, associated with a first NOC interconnect stage of the NOC interconnect, receiving the source synchronous clock signal and outputting a delayed source synchronous clock signal;
• a local pulse generator, associated with the first NOC interconnect stage, receiving the delayed source synchronous clock signal, and generating a first pulse in response to a first phase of the delayed source synchronous clock signal and generating a second pulse in response to a second phase of the delayed source synchronous clock signal;
• a flop-repeater circuit, associated with the first NOC interconnect stage, capturing and launching data received from the source circuit in response to each of the first pulse and the second pulse;
• and
• a local offset circuit, associated with the first NOC interconnect stage, receiving the delayed source synchronous clock signal and providing a de-skewed source synchronous clock signal.

A system comprising:

• a first functional block coupled to a source circuit;
• a second functional block coupled to a sink circuit;
• and
• a network-on-chip (NOC) interconnect for transmitting data from the source circuit to the sink circuit, wherein the NOC interconnect is clocked using a source synchronous clock signal, the NOC interconnect comprising:
• a first NOC interconnect stage, to receive data from the source circuit, comprising:
• (1) a local programmable delay circuit to receive the source synchronous clock signal and output a delayed source synchronous clock signal, (2) a local pulse generator to receive the delayed source synchronous clock signal and generate a first pulse in response to a first phase of the delayed source synchronous clock signal and generate a second pulse in response to a second phase of the delayed source synchronous clock signal, (3) a flop-repeater circuit to both capture and launch data received from the source circuit in response to each of the first pulse and the second pulse, and (4) a local offset circuit, wherein the local offset circuit is configured to receive the delayed source synchronous clock signal and provide a de-skewed source synchronous clock signal, and
• a second NOC interconnect stage to receive the launched data from the flop-repeater circuit and the de-skewed source synchronous clock signal from the local offset circuit, wherein data is transmitted across the NOC interconnect during each of two phases of a clock signal for a corresponding NOC interconnect stage, allowing transmission of the data across the NOC interconnect at twice the rate possible with transmission of data during only one of the two phases of the clock signal.