Sample-and-hold circuit and analog-to-digital converter circuit including the same

A sample-and-hold circuit comprising:

• a first differential input terminal configured to receive a first differential input voltage among differential input voltages;
• a second differential input terminal configured to receive a second differential input voltage among the differential input voltages, which is different from the first differential input voltage;
• a first unity gain buffer configured to receive the first differential input voltage from the first differential input terminal and to output a first differential output voltage to a first differential output terminal;
• a second unity gain buffer configured to receive the second differential input voltage from the second differential input terminal and to output a second differential output voltage to a second differential output terminal;
• a first feedback switch having one terminal connected to an output terminal of the first unity gain buffer;
• a second feedback switch having one terminal connected to an output terminal of the second unity gain buffer and the other terminal connected to the first feedback switch;
• and
• an amplifier having a first input terminal connected to the first and second feedback switches, a second input terminal receiving a reference voltage, and an output terminal outputting a feedback voltage that regulates outputs of the first and second unity gain buffers;
• and
• a sampling capacitor connected to the first input terminal of the amplifier.

An analog-to-digital converter (ADC) circuit comprising:

• a plurality of sub-ADCs configured to convert analog signals into digital signals in a time-interleaving method;
• and
• a sample-and-hold circuit configured to repeatedly sample and buffer a first differential input voltage among differential input voltages by using a first unity gain buffer, and repeatedly sample and buffer a second differential input voltage among the differential input voltages, wherein the second differential input voltage is different from the first differential input voltage by using a second unity gain buffer,
• wherein
• in response to the first and second differential input voltages being sampled, the sample-and-hold circuit is configured to input a common mode voltage generated by connecting output terminals of the first unity gain buffer and the second unity gain buffer, to an amplifier and to regulate outputs of the first and second unity gain buffers based on the common mode voltage and a reference voltage, and
• in response to the first and second differential input voltages being buffered, the sample-and-hold circuit is configured to provide the regulated outputs of the first and second unity gain buffers to the sub-ADCs.