Method and apparatus for controlling second harmonic-of power amplifier in wide frequency range

An apparatus comprising:

• a first pair of transistors configured to receive a first voltage input and a second voltage input respectively at their gate terminals;
• a second pair of transistors comprising respective sources coupled to respective drains of the first pair of transistors, the second pair of transistors being configured to provide a differential voltage signal based on the first voltage input and the second voltage input;
• a transformer comprising a primary winding and a secondary winding, the primary winding being coupled to respective drains of the second pair of transistors to receive a current signal associated with the differential voltage signal, the primary winding comprising a midpoint that separates the primary winding to two sections with equal resistances, the secondary being coupled between a ground terminal and an output terminal;
• and
• at least a programmable capacitor coupled between the midpoint of the primary winding and a first common node that is coupled to the first pair of transistors;
• wherein the differential voltage signal comprises a frequency range from 1 MHz to 19 GHz.

A method for suppressing second harmonic in wideband power amplifier, the method comprising:

• configuring a first pair of transistors to have respective two gates to receive a first voltage input and a second voltage input respectively;
• configuring a second pair of transistors to provide a differential voltage signal based on the first voltage input and the second voltage input;
• providing a transformer comprising a first winding and a second winding, the first winding comprising a midpoint that separates the first winding to two sections with equal resistances;
• coupling the first winding between respective drains of the second pair of transistors to receive a current signal associated with the differential voltage signal;
• coupling the second winding between a ground terminal and an output terminal;
• coupling at least a programmable capacitor between the midpoint of the first winding and a first common node that is coupled to respective sources of the first pair of transistors, the programmable capacitor being configured to allow capacitance adjustment from 0.1 pF to 10 μF;
• coupling a power supply to a second common node of the center-tap line that is connected to the midpoint of the first winding via a first resistor and connected to the programmable capacitor via a second resistor;
• and
• coupling the first common node to the programmable capacitor via a third transistor and to ground via a fourth resistor.